Semiconductor Process for High-Voltage and Low-Voltage Device Integration
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Solution Overview
Problem
Conventional semiconductor processes for integrating memory cells and other devices cause substrate defects in low-voltage device areas due to stress from forming thicker gate oxide layers required by high-voltage devices, leading to device leakage issues.
Innovation Solution
A semiconductor process where a patterned charge-trapping layer is formed to expose high-voltage and low-voltage device areas separately, allowing for distinct gate oxide layer thicknesses without inducing stress in the low-voltage area, by forming a thicker gate oxide layer only in the high-voltage area and a thinner layer in the low-voltage area, preventing substrate defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thicker gate oxide layer is formed in the low-voltage device area to match the high-voltage device requirements, then the high-voltage device performance is improved, but substrate defects and device leakage occur in the low-voltage device area
Solution Approach 1:
The patent applies local quality by forming a thicker gate oxide layer specifically in the high-voltage device area while maintaining a thinner gate oxide layer in the low-voltage device area. This is achieved through selective formation processes that deposit or grow the gate oxide layer with different thicknesses in different regions, allowing each area to have the optimal gate oxide thickness for its specific device type without causing harmful stress effects in the low-voltage area.
2Manufacturing precision
If separate formation steps are used for different gate dielectric layers in high-voltage and low-voltage device areas, then the required gate dielectric thicknesses are achieved, but process complexity increases and stress-induced defects occur
Solution Approach 1:
The patent merges the formation of different thickness gate oxide layers into a single integrated process step. Instead of separately forming thick gate oxide in high-voltage areas and thin gate oxide in low-voltage areas through multiple sequential steps, the invention uses a unified deposition or growth process that simultaneously creates the appropriate thickness distribution across different device areas, reducing process complexity while maintaining precise thickness control.
Data Source
AI summary
A semiconductor process is described. A semiconductor substrate having a memory area, a first device area and a second device area is provided. A patterned charge-trapping layer is formed on the substrate, covering the memory area and the second device area but exposing the first device area. A first gate oxide layer is formed in the first device area. The charge-trapping layer in the second device area is removed. A second gate oxide layer is formed in the second device area.