3D Semiconductor Memory Device Well Region Voltage Control
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Solution Overview
Problem
The transition to 3D semiconductor memory devices presents challenges in reliably manufacturing and achieving efficient operating characteristics, particularly in read operations, due to the complexity of vertically stacked cell transistors.
Innovation Solution
A 3D semiconductor memory device design that includes pass transistor groups sharing well regions, with a controller applying specific voltages to these regions during read operations to bi-directionally drive selection transistors and uni-directionally drive memory cells, improving read operation speed and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically stacked cell transistors are used to increase integration density, then storage capacity is improved, but manufacturing reliability and operating efficiency deteriorate
Solution Approach 1:
The pass transistor groups are divided into multiple independent groups, each sharing a specific well region. This segmentation allows independent voltage control of each well region, enabling selective activation of transistor groups to improve manufacturing reliability and operating efficiency while maintaining high integration density through vertical stacking
2Quantity of substance
If vertically stacked cell transistors are used to increase integration density, then storage capacity is improved, but operating efficiency deteriorates
Solution Approach 1:
The controller dynamically applies different voltages to different well regions based on read operation requirements. By selectively activating specific pass transistor groups through voltage control, the system optimizes read operation speed and efficiency while maintaining the high integration density achieved through vertical transistor stacking
3Speed
If pass transistor groups share well regions with differential voltage control, then read operation speed is improved, but device complexity increases
Solution Approach 1:
Multiple pass transistor groups share common well regions and can be selectively activated through differential voltage control. This multi-functional design allows the same physical structure to serve multiple read operation pathways, improving read speed while avoiding the need for completely separate transistor structures for each read path
Data Source
AI summary
A three-dimensional (3D) semiconductor memory device comprises memory cell strings each comprising at least one selection transistor and at least one memory cell, a first pass transistor group sharing a first well region and comprising a first selection line pass transistor connected to the selection transistor and a first world line pass transistor connected to the memory cell, a second pass transistor group sharing a second well region and comprising a second selection line pass transistor connected to the selection transistor, and a controller that controls the first pass transistor group and the second pass transistor group. The controller applies selected voltages to the first and second well regions during read operation.