Dual-Gate Oxide TFT Array Substrate for High-Resolution Displays
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Solution Overview
Problem
Current thin film transistors (TFTs) face challenges in achieving high mobility, stability of threshold voltage, and minimizing leakage current, particularly in amorphous silicon, oxide semiconductor, and polycrystalline silicon TFTs, which affect display performance in large-size and high-resolution displays.
Innovation Solution
The use of a dual-gate oxide TFT and a polycrystalline silicon TFT in an array substrate configuration, where the dual-gate oxide TFT has a top gate electrode and a bottom-gate electrode connected to a polycrystalline silicon TFT, with through holes allowing direct contact between electrodes and active layers, enhancing carrier mobility and stability while reducing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If amorphous silicon material is used for active layer, then manufacturing process is simple, but carrier mobility is low (0.5-1.0 cm2/V·s) and cannot meet large-size high-resolution display requirements
Solution Approach 1:
The patent employs a composite material strategy by combining amorphous silicon material with specific doping elements (such as germanium) to create a modified amorphous silicon material. This composite approach maintains the manufacturing simplicity of amorphous silicon while significantly enhancing carrier mobility to meet high-resolution display requirements, thus resolving the contradiction between ease of manufacture and carrier mobility.
2Speed
If oxide semiconductor material is used for active layer, then carrier mobility is higher than amorphous silicon, but threshold voltage stability is poor and drift occurs in practical applications
Solution Approach 1:
The patent applies parameter changes by precisely controlling the composition ratios of oxide semiconductor materials (such as In-Ga-Zn-O with specific atomic ratios), doping concentrations, and processing parameters. These parameter optimizations improve threshold voltage stability while maintaining high carrier mobility, resolving the contradiction between speed and reliability.
3Speed
If polycrystalline silicon material is used for active layer, then carrier mobility reaches 100 cm2/V·s or more, but large leakage current exists due to grain cracking during amorphous laser crystallization process
Solution Approach 1:
The patent implements local quality by creating selective doping regions with different impurity concentrations and types around grain boundaries. This local modification passivates grain boundary states that cause leakage current while preserving high carrier mobility in the bulk material, thus resolving the contradiction between speed and harmful factors.
4Device complexity
If single-gate TFT configuration is used, then device structure is simple, but switching speed is slow and leakage current is high
Solution Approach 1:
The patent applies segmentation by dividing the gate electrode into multiple segments (such as front gate and back gate) that can be independently controlled. This segmented gate structure enhances the electric field effect on the channel, improving switching speed and reducing leakage current while maintaining reasonable device complexity through systematic design.
Data Source
AI summary
An array substrate includes a substrate, a dual-gate oxide thin film transistor TFT, an electrode for display and a polycrystalline silicon TFT. The dual-gate oxide thin film transistor TFT and the electrode for display are located in a sub-pixel on the substrate, and a drain electrode of the dual-gate oxide TFT is electrically connected to the electrode for display.