3D Memory Device Insulating Structure for Etch Gouging Control
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Solution Overview
Problem
The challenge in 3D NAND memory devices is the gouging variation during etching of slit openings, which leads to damage in the staircase region and complexity in fabrication, especially with semiconductor plugs grown at the sidewall, requiring precise control of etch depth across different film structures.
Innovation Solution
A trench filled with sacrificial material is used as an etch stop layer and buffer to balance etch loading between the core array and staircase regions, and the trench and slit opening are filled with dielectric materials to form an insulating structure, allowing for uniform substrate thinning and reducing fabrication complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If semiconductor plugs are grown at the sidewall with precise etch depth control, then memory device performance is improved, but fabrication complexity increases due to gouging variation during etching
Solution Approach 1:
A trench filled with sacrificial material is introduced as an intermediary structure between the core array and staircase regions. This trench acts as a buffer that absorbs etch loading variations and prevents gouging during the etching process, thereby maintaining etch depth control without increasing fabrication complexity
Solution Approach 2:
The substrate is segmented into distinct regions: a core array region, a staircase region, and an intermediate trench region. This segmentation allows each region to be optimized independently, with the trench serving as a buffer zone that isolates the etching processes and prevents interference between regions
2Manufacturing precision
If trench filled with sacrificial material is used as etch stop layer, then gouging variation is compensated, but device structure becomes more complex
Solution Approach 1:
The trench filled with sacrificial material serves as a mediator structure that compensates for gouging variation. By positioning this trench between the core array and staircase regions, it absorbs etch loading differences and prevents direct interaction between the two regions during etching, thereby compensating for gouging without requiring complex structural modifications
Solution Approach 2:
The etch loading parameter is changed by introducing the trench structure. This structural modification alters the etch dynamics, creating a buffer zone that equalizes etch rates across different regions and compensates for gouging variation that would otherwise occur during the etching process
3Productivity
If uniform substrate thinning is achieved, then production yield increases, but fabrication process becomes more challenging
Solution Approach 1:
The trench structure is formed in advance before the thinning process. This preliminary action creates a built-in reference structure that guides the thinning process, ensuring uniform material removal across the substrate. The trench acts as a stop marker that prevents over-thinning and ensures consistent thickness throughout the substrate
Solution Approach 2:
The trench structure serves a dual purpose: it acts as both a structural element and a reference marker for the thinning process. During thinning, the trench automatically provides feedback on the remaining thickness, allowing the process to self-regulate and achieve uniform thinning without requiring complex external monitoring or adjustment mechanisms
Data Source
AI summary
Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a peripheral circuit on the substrate, a memory stack including interleaved conductive layers and dielectric layers above the peripheral circuit, a first semiconductor layer above the memory stack, a second semiconductor layer above and in contact with the first semiconductor layer, a plurality of channel structures each extending vertically through the memory stack and the first semiconductor layer, and an insulating structure extending vertically through the memory stack, the first semiconductor layer, and the second semiconductor layer.