3D Semiconductor Memory Structure for Higher Integration
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the expensive equipment required for fine pattern formation, making it difficult to increase their density, and three-dimensional semiconductor memory devices are proposed to overcome this limitation.
Innovation Solution
A semiconductor memory device with a three-dimensional structure is fabricated by alternately stacking interlayer dielectric layers, etching to form grooves, and creating recessed regions for semiconductor patterns, which allows for increased integration and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices are used with fine pattern formation, then integration density can be increased, but expensive processing equipment is required
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertically stacked memory cells. Multiple memory cell layers are stacked in the vertical direction, allowing integration density to increase without requiring finer lateral patterning. This dimensional change enables higher density while avoiding the need for expensive fine-patterning equipment.
2Quantity of substance
If three-dimensional semiconductor memory devices are fabricated with complex stacking processes, then integration is increased, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming sacrificial patterns, creating recessed regions, filling with conductive materials, and removing sacrificial patterns. Each stage is independently manageable, allowing complex three-dimensional structures to be built through simple, repeatable steps that reduce overall fabrication complexity.
Solution Approach 2:
Sacrificial patterns are formed in advance to define the positions of recessed regions before the actual memory cell structures are built. This preliminary action simplifies subsequent fabrication steps by pre-establishing the spatial framework for vertical stacking, reducing the complexity of the overall process.
3Quantity of substance
If more semiconductor patterns are formed to increase integration, then productivity may decrease due to longer fabrication time
Solution Approach 1:
Multiple memory cell layers are combined in a single vertical stack, allowing multiple functional units to be formed simultaneously through one fabrication process. This merging approach increases the number of semiconductor patterns without proportionally increasing fabrication time, thereby maintaining or improving productivity.
Solution Approach 2:
The sacrificial patterns automatically define the positions and dimensions of recessed regions through self-aligned processes. This self-service mechanism eliminates the need for additional alignment and positioning steps, enabling faster fabrication of multiple semiconductor patterns while maintaining precision.
Data Source
AI summary
Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.