3D Memory Interconnect Layout With Through-Contacts and Dummy Contacts

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Solution Overview

Problem

Existing semiconductor devices face challenges in increasing data storage capacity and improving reliability and productivity, particularly in three-dimensional memory cell arrangements.

Innovation Solution

A semiconductor device design featuring a first structure with a substrate and circuit devices, and a second structure with a conductive plate layer, gate electrodes, channel structures, through-contact plugs, and an upper interconnection structure that includes bitlines, contacts, and dummy contacts, enhancing electrical connectivity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are arranged three-dimensionally to increase data storage capacity, then storage capacity is improved, but device complexity increases

Engineering Contradiction:
Improvedata storage capacityVSAvoidstructural complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple layers of memory cells vertically. This includes forming alternating layers of first and second channel structures with corresponding gate structures, enabling increased storage capacity by utilizing the vertical dimension for additional memory layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where first channel structures and second channel structures are interleaved with first gate structures and second gate structures in alternating layers. The through-contacts penetrate through multiple nested layers to establish electrical connections, creating a compact multi-layered memory architecture.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Reliability

If through-contacts are formed to penetrate sacrificial insulating layers for electrical connection, then electrical connectivity is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent employs sacrificial insulating layers that are formed in advance during the manufacturing process. These sacrificial layers are strategically positioned and removed at predetermined stages to create pathways for through-contacts, ensuring proper alignment and connection before final assembly. This preliminary structuring simplifies subsequent through-contact formation.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial insulating layers serve as temporary intermediary structures that facilitate the formation of through-contacts. These layers are formed, patterned, and removed in controlled sequences to enable precise through-contact placement without requiring direct high-precision alignment operations, thus improving manufacturing feasibility.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If dummy contacts are added to the interconnection structure, then productivity is improved, but device complexity increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidinterconnection complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The dummy contacts are designed to have the same structural characteristics as functional through-contacts, allowing them to be formed using identical manufacturing processes. This multi-functionality approach enables the same fabrication techniques to produce both operational and dummy contacts, streamlining the manufacturing process and improving productivity through process standardization.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20260047418A1Semiconductor devices and data storage systems including the same
Publication Date: 2026.02.12 SAMSUNG ELECTRONICS CO LTD
  • US20260047418A1 patent drawing
  • US20260047418A1 patent drawing
  • US20260047418A1 patent drawing

AI summary

A semiconductor device includes a first structure including a substrate, circuit devices, a lower interconnection structure electrically connected to the circuit devices, and a second structure on the first structure. The second structure includes a conductive plate layer; gate electrodes on the conductive plate layer and extending in a first direction; separation regions penetrating through the gate electrodes and extending in the first direction; channel structures penetrating through the gate electrodes and respectively including a channel layer; through-contact plugs spaced apart from the gate electrodes and extending in the vertical direction to be electrically connected to the lower interconnection structure of the first structure; first and second contacts electrically connected to the channel layer and the through-contact plugs, respectively; bitlines electrically connecting at least one of each of the first and second contacts to each other; and dummy contacts connected to the bitlines and spaced apart from the through-contact plugs.