3D Memory Array Layout for High Density and Lower Interplane Capacitance
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Solution Overview
Problem
Current 3-D memory arrays face limitations in memory cell density and capacitance, leading to reduced storage efficiency and increased disturbances between adjacent floors.
Innovation Solution
The implementation of a 3-D memory array design featuring a staggered arrangement of conductive contacts and alternating layers of conductive and insulation materials, with serpentine-shaped trenches and chalcogenide storage elements, increases memory cell density and reduces capacitance between floors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased, then storage efficiency is improved, but capacitance between adjacent floors increases causing disturbances
Solution Approach 1:
The patent transitions from a planar 2D memory array to a three-dimensional stacked architecture with multiple floors separated by insulation layers. This vertical stacking allows increased memory cell density while the insulation layers between floors reduce capacitance coupling and disturbances between adjacent memory planes.
Solution Approach 2:
Insulation layers are introduced as intermediary elements between adjacent conductive floors to reduce parasitic capacitance and electrical disturbances. These insulation layers act as mediators that electrically isolate the floors while allowing the stacked structure to maintain high density.
2Quantity of substance
If conventional 3-D memory array design is used, then manufacturing is simplified, but memory cell density per conductive line is limited
Solution Approach 1:
The patent implements a three-dimensional stacked memory array where memory cells are arranged across multiple vertical floors rather than a single plane. This allows each conductive line to access memory cells across multiple floors, effectively doubling the memory cell density per conductive line compared to conventional 2D arrays.
Solution Approach 2:
The memory array is segmented into multiple independent floors separated by insulation layers, with each floor containing complete sets of word lines, bit lines, and memory cells. This segmentation allows each conductive line to serve multiple floors while maintaining independent operation of each floor.
Data Source
AI summary
An example three-dimensional (3-D) memory array includes a substrate material including a plurality of conductive contacts arranged in a staggered pattern and a plurality of planes of a conductive material separated from one another by a first insulation material formed on the substrate material. Each of the plurality of planes of the conductive material includes a plurality of recesses formed therein. A second insulation material is formed in a serpentine shape through the insulation material and the conductive material. A plurality of conductive pillars are arranged to extend substantially perpendicular to the plurality of planes of the conductive material and the substrate and each respective conductive pillar is coupled to a different respective one of the conductive contacts. A chalcogenide material is formed in the plurality of recesses such that the chalcogenide material in each respective recess is formed partially around one of the plurality of conductive pillars.