Solid-State Devices TRIZ Cases

A quarter-wave plate and band-pass polarizer cut ambient-light reflection while preserving OLED and micro LED light output.

A graded p-type base and high-concentration channel region suppress electric field concentration and punch-through in trench-gate MISFETs.

A conductive light-shielding layer linked through buffer via-holes simplifies etching, cuts defects, and improves top-gate TFT electrical stability.

A necked conductive joint and cured protective surround improve LED-to-substrate connection yield and durability against moisture and heat.

A curved overlapping conductive structure balances current flow and parasitic capacitance to reduce feedthrough voltage, flicker, and image sticking.

Separate local interconnect lines isolate read and write port currents in dual-port SRAM, balancing ground bounce and stabilizing operation.

A condensed cyclic carbene organometallic compound suppresses triplet exciton loss, improving green OLED stability, efficiency, and lifespan.

Light pipe cavities and optical filters in a BSI image sensor block excitation light, cut crosstalk, and improve emissive light collection.

Sorting microLED tiles by size, edge straightness, and squareness improves registration pitch and display uniformity without slowing assembly.

A non-n nitride layer neutralizes contaminated regrowth interfaces in stacked micro LED structures, preserving hole injection and light emission efficiency.

A three-layer insulating film around the light emitting stack reduces surface defects and short circuits, improving display reliability and efficiency.

A thin detection region with resin support and a thicker peripheral frame suppresses crosstalk while protecting the detector during handling.

A GaPN intermediate passivation layer cuts lattice mismatch and defects, helping small sub-pixels maintain uniform red and blue emission.

Selective roughening in the pixel center limits light escape, reducing cross-talk while preserving current flow and illuminance uniformity.

A bonding substrate with light-blocking regions helps micro LED modules scale to larger displays while reducing seam visibility and light refraction.

Anisotropic etching with a hard mask improves micro LED pixel sidewall flatness, cuts dicing loss, and supports smaller pixel spacing.

A third branched electrode connects inorganic LEDs in series to improve voltage division, cut line-resistance loss, and ease TFT sizing.

A sealing layer and low-profile dams improve substrate alignment while blocking water and oxygen intrusion in flat display panels.

Sequential etching with insulating sidewall protection reduces active-layer damage and short-circuit risk in light-emitting elements.

Combining UV, visible, and near-IR LEDs with wavelength converters, this lighting case adds vitamin D support and cell activation to illumination.

An integrated diode and deep trench isolation create an alternative U-shaped current path that cuts loop inductance and switching loss.

Active region width and fin-count balancing helps n-type and p-type FinFETs achieve matched driving strength and lower current resistance drops.

Using on-substrate LEDs to cure light-curable ink cuts external UV steps while a sealed inert chamber limits unspecific curing and improves yield.

Light-blocked pixels generate correction signals that remove dark current and offset noise from event-based image sensor outputs.

Clock terminals linked across chips on a common substrate cut jitter and enable synchronized high-speed operation with lower power and area.

Multi-wavelength LEDs with sub-500 ps response enable full-duplex optical wireless links beyond 20 Gbps while avoiding radio bandwidth limits.

A multi-quantum well LED generates white light on one chip without phosphors, reducing Stoke's shift loss and aiding faster visible light communication.

Patterned retardation and cholesteric reflective layers suppress pixel crosstalk and keep multispectral image tint uniform.

A stable temporary fixing resin enables wafer bonding on uneven surfaces and clean mechanical peeling without solvent, heat, or laser steps.

By extending the light-emitting layer beyond conductive-layer edges, this micro-LED chip reduces surface recombination and improves emission.

Comparator enable gating with a ramp reference reduces CMOS image sensor ADC power use while preserving efficient pixel signal conversion.

Opposite semiconductor stacking and binder fixing align light-emitting elements between electrodes without an electric field, improving display fabrication.

Layered MOSFET zones and a sidewall gate improve IR absorption impedance matching while preserving drain-source current and signal-to-noise ratio.

Partition layers and pixel separation layers suppress optical cross-talk, helping miniaturized image sensors capture clearer images in low light.

A patterned dielectric metasurface boosts infrared absorption in miniaturized semiconductor sensors without increasing sensor size.

A separation groove lined with a hydrogen block layer protects oxide semiconductor charge transfer paths, reducing defects, noise, and instability.

Separating photoelectric conversion and charge storage into two diffusion regions boosts dynamic range while reducing dark current.

Conductive bonding layers join modular display substrates without wire bonding, improving color uniformity and removing visible black lines.

Specific host and dopant blends improve charge balance and delayed fluorescence in OLED emission layers, boosting efficiency and life.

Microstructure holes in thin-silicon CMOS photosensors boost photon absorption and EQE while preserving fast rise time for 3D imaging.

Short-duration RTA and dual hydrogen barriers enable perovskite memory capacitors to integrate with logic without high-temperature damage.

A gate line that doubles as a light shield and a 3D TFT channel layout raise pixel aperture ratio without sacrificing resolution or stability.

Omitting photoresist baking reduces signal-line slope, improves insulating-layer coverage, and supports narrower display bezels.

An oxide 2-DEG vertical channel with oxygen vacancies reduces ferroelectric interface traps, improving memory endurance and low-voltage operation.

An insulation-post capacitor layout replaces deep high-aspect-ratio holes to preserve capacitance while easing size control and improving electrical properties.

A porous semiconductor layer beside trench isolation cuts substrate leakage and harmonics in bulk-substrate RF switches at lower cost.

Light-triggered dispersant breakdown enables low-temperature removal after electric-field alignment, reducing residue defects in display fabrication.

A single receiver and image selection circuit choose the best sensor data by noise, dynamic range, or face criteria to cut imaging complexity.

Layered dielectrics with etched lateral exposure and non-parallel sidewalls curb charge leakage while strengthening node isolation.

Unequal slit-end light-transmitting regions balance weak zones in pixel electrodes, reducing afterimages, horizontal stripes, and Trace Mura.

Spatial contact-angle regions and gradients guide droplet actuation in digital microfluidics without surfactants, protecting biological molecules.

A non-emissive micro-LED region overlaps adjacent emitters to offset sidewall etching damage and preserve luminous efficiency in dense displays.

A two-layer flattening film isolates resin spacers from contact-hole thickness variation, keeping substrate spacing accurate and stable.

Through-stack contacts and adjacent strapping structures support staircase tiers, cutting collapse risk and parasitic capacitance in vertical memory arrays.

Vertical complementary NFET/PFET stacking across adjacent SRAM cells cuts cell area while preserving functionality in dense IC layouts.

Parallel same-layer power lines and direct switch-driver connection cut via resistance, stabilizing local logic supply and delay time.

Reflective cavity walls and a form-fitted carrier-package structure shrink packaged microLEDs to micrometer scale while preserving connectivity.

Half-cut grooves formed before plasma etching reduce thick base material removal time and help keep wafer dicing surfaces clean.

Hydrophilic well sidewalls with a partial hydrophobic cover keep OLED ink from climbing edges, producing more uniform printed layers.

A staggered-contact, serpentine-layer 3D memory array doubles cell density per line while reducing capacitance disturbances between floors.

Dummy holes through contact insulating layers vent hydrogen near oxide transistors, limiting threshold shifts and improving panel reliability.

Metal-filled through holes connect LTPO TFT active layers without later process damage, simplifying fabrication and improving connection reliability.

One-time patterning puts signal lines, connecting bridges, and TFT layers together to cut resistance, remove via holes, and improve stretchability.

An IR sensor behind a semi-transparent reflective patch preserves indicator visibility while enabling sensitive proximity input.

Unequal trench gate depths suppress potential dips, enabling smoother charge transfer and more reliable imaging in thicker semiconductor layers.

Varying color-filter-to-photodiode depth enables long- and normal-exposure signals in one shot, improving dynamic range and imaging speed.

Covering peripheral slits with a cladding layer helps stop cutting-induced cracks and blocks foreign substances in display substrates.

Closed-loop polygonal electrodes shape the electric field to self-align light emitting elements and reduce defects in micro-scale displays.

A 3D stacked QIS separates jot arrays, readout, and processing layers to raise bandwidth, cut power, and support low-noise high-speed imaging.

Frame-dependent neutralizing charge offsets dark current in radiation detector capacitors, improving photo current accuracy and reducing image distortion.

Boron-containing polycyclic aromatic compounds improve OLED charge recombination, raising luminous efficiency and quantum efficiency at low driving voltage.

Patterned marks within pixel regions replace dedicated alignment marks, preserving micro-LED array substrate space while maintaining transfer alignment.

Transition layers in a dual-deck 3D NAND stack improve upper-lower channel overlap and prevent word line voids, leakage, and shorts.

A 3D word line layout increases effective width while dielectric isolation cuts parasitic capacitance for faster ferroelectric memory operation.

Placing the capacitor electrode in the subpixel area increases storage capacitance and reduces layout interference to improve touch accuracy.

Undercut grooves, holes, and concave substrate regions improve light transmittance while preserving thin display panel integration.

Asymmetric edge bank surfaces stabilize the light conversion layer while blocking moisture ingress in emission and dummy opening areas.

Conductive masses bridge upper and lower channel strings in a 3D memory array to cut interface resistance and improve electrical coupling.

Strategic photo sensor placement and a pinhole array cut in-display fingerprint sensing cost and thickness while using pixels as light sources.

An epitaxial boron passivation layer suppresses dangling-bond dark current in vertical transfer gates while preserving pixel sensitivity.

A single-flight stair-step layout gives 3D NAND wordlines reliable electrical access while cutting masking steps and structural complexity.

A tapered dielectric placeholder guides self-aligned backside source/drain contacts, reducing voids, alignment errors, and contact resistance.

End-positioned contact portions keep electrical connection away from light paths, reducing light loss and improving display brightness.

Enclosed transmitter and receiver spaces use sealed light passages and shielding to block dirt and ambient light in compact proximity sensors.

A shaped transparent sidewall and direct reflection layer redirect lateral light in micro-LED chips to boost forward brightness after packaging.

Patterned barrier layers and insulated series interconnects cut light absorption in high-voltage monolithic LED chips while preserving filament-like emission.

Alternating third and fourth voltage lines improve pixel voltage uniformity, reducing voltage drop, luminance deviation, and crosstalk.

Guiding and alignment structures enable accurate micro LED epitaxial pick-up, reducing chip shift, misplacement, and bonding damage.

Fluorine-doped ULK boundary dents and planarization prevent gaps between MRAM and logic regions, preserving surface flatness and integrity.

Wet etching replaces metal-mask limits in micro-LED panels, while reflective barriers between quantum dots suppress optical crosstalk.

Dynamic repartitioning in stacked 3D memory maps out error regions, preserving usable dies while sustaining bandwidth and power efficiency.

Staggered wiring regions and meandering signal lines cut diffraction while preserving electrical connectivity and transparent viewing.

Polarization-based correction removes reflected and diffracted light in under-display cameras, preserving image quality while enabling narrower bezels.

Alternating wiring layers at different heights reduce parasitic coupling and image interference in compact narrow-bezel displays.

A single-lithography self-aligned process improves vertical device alignment and hermetic substrate bonding while reducing fabrication cost.

Segmented light-blocking openings cut electrode reflection while preserving emitted light efficiency and pixel visibility in LED displays.

Series-connected light-emitting elements raise pixel voltage to cut power loss in the driver and boost micro-LED display luminance.

A dual-wavelength blue LED enables high and low blue modes in RGB emissive displays without a fourth subpixel, cutting complexity and cost.

Segmented gate layers and trench isolation create mixed-voltage field effect transistors at high density with simpler thickness control.