3D Stacked Memory Repartitioning for Error Region Isolation
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Solution Overview
Problem
Current semiconductor memory technologies face a mismatch in performance with modern host processors, leading to inefficiencies such as high idle times and a compromise between memory subsystem performance and density, with limitations in memory bandwidth and power optimization, and a need for frequent interface redesigns due to evolving technologies.
Innovation Solution
The implementation of a stacked-die 3D memory architecture with shared control logic and memory vaults that enable concurrent data transfer, a standardized host processor interface, and dynamic reconfiguration to adapt to changing technologies, along with error tracking and repartitioning to optimize energy efficiency and memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional semiconductor memory technology is used, then current manufacturing processes can be maintained, but performance mismatch with modern host processors occurs and idle time increases
Solution Approach 1:
The patent transitions from planar 2D memory architecture to three-dimensional stacked memory architecture, enabling vertical stacking of memory dies and logic layers. This dimensional change dramatically increases memory density and bandwidth while reducing the physical footprint, directly addressing the performance bottleneck without increasing processor idle time
Solution Approach 2:
The patent integrates memory and logic functions into a single stacked package, merging previously separate memory chips and controller chips into one unified three-dimensional structure. This integration reduces communication latency and increases effective memory performance while utilizing the vertical space efficiently
2Speed
If higher bandwidth memory subsystems are implemented, then data transfer speed improves, but the number of memory cards that can be connected is limited by electrical specifications
Solution Approach 1:
The stacked memory architecture utilizes the vertical dimension to achieve high bandwidth through multiple simultaneous data paths between stacked memory dies and logic layers, eliminating the need to increase the number of horizontal connection cards while maintaining high data transfer speeds
Solution Approach 2:
The memory system is segmented into multiple independent stacked modules, each capable of operating autonomously. This segmentation allows multiple memory stacks to be connected in parallel, increasing system capacity and bandwidth without exceeding electrical specification limits on individual cards
3Quantity of substance
If memory density is increased, then storage capacity improves, but performance is compromised
Solution Approach 1:
By stacking multiple memory dies vertically, the system achieves high density in the vertical dimension while maintaining short signal paths and low latency. The three-dimensional architecture allows dense packing of memory cells without increasing the horizontal footprint or degrading performance
Solution Approach 2:
Memory and logic layers are merged into a single stacked package, with logic layers positioned adjacent to memory dies they control. This proximity reduces access latency and enables high-density configuration without compromising performance
4Speed
If interface standards are extended to increase bandwidth, then data transfer capability improves, but power optimization is lost and redesign is needed as technologies evolve
Solution Approach 1:
The stacked memory architecture employs dynamic power management where logic layers can be selectively activated or deactivated based on access patterns. The short vertical interconnects enable rapid switching between active and low-power states, optimizing power consumption while maintaining high data transfer capability when needed
Solution Approach 2:
The standardized stacked package interface can accommodate different memory technologies and capacities while maintaining the same form factor and connection protocol. This multi-functionality allows the system to adapt to evolving technologies without requiring redesign of the interface architecture
Data Source
AI summary
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for repartitioning the stack of memory dies and storing the new partitions in a memory map. Repartitioning in selected configurations allows portions of memory to be removed from use without affecting the rest of the memory device. Additional devices, systems, and methods are disclosed.