Ferroelectric Memory Word Line Layout for Lower Resistance
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Solution Overview
Problem
Existing ferroelectric memory devices face issues with high word line resistance and high bit line/source line to word line capacitance due to the limited width of the word line structure and undesired overlapping, which affects their operational efficiency and speed.
Innovation Solution
A memory device design featuring word line structures with a cross-sectional shape, isolated from bit line and source line structures by dielectric structures, which reduces parasitic capacitance and increases the equivalent width of the word line, thereby decreasing resistance and enhancing operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the word line structure width is increased, then the word line resistance decreases, but the overlapping with bit line and source line structures increases, leading to higher parasitic capacitance
Solution Approach 1:
The word line structure transitions from a conventional planar configuration to a three-dimensional configuration by extending upward from the substrate surface. This vertical extension allows the word line to achieve greater effective width and lower resistance without increasing its lateral footprint, thereby avoiding overlap with bit line and source line structures and reducing parasitic capacitance.
Solution Approach 2:
The bit line and source line structures are positioned to overlap with the horizontal projection of the word line structure, creating a nested spatial arrangement. This nesting allows the word line to achieve greater effective width for lower resistance while the vertical separation and dielectric structures prevent actual contact, maintaining low parasitic capacitance.
2Speed
If the word line structure width is increased, then the operational speed improves, but the parasitic capacitance increases due to overlapping
Solution Approach 1:
The word line structure extends vertically from the substrate surface, creating a three-dimensional configuration. This vertical extension increases the effective width of the word line for faster operation without increasing lateral dimensions, thereby avoiding overlap with bit line and source line structures and preventing increased parasitic capacitance.
3Object-affected harmful factors
If dielectric structures are added to isolate word line from bit line and source line, then parasitic capacitance decreases, but device complexity increases
Solution Approach 1:
The dielectric structures serve multiple functions: they electrically isolate the word line from bit line and source line structures to reduce parasitic capacitance, provides mechanical support for the elevated word line configuration, and define the vertical spacing in the three-dimensional structure. This multi-functionality reduces the need for additional specialized components.
Data Source
AI summary
A semiconductor device includes a plurality of ferroelectric memory cells arranged over a substrate. Each of the plurality of ferroelectric memory cells includes: a first conductive structure extending along a first lateral direction and having a central portion and a pair of side portions, the side portions respectively extending away from the central portion along a second lateral direction perpendicular to the first lateral direction; a ferroelectric layer disposed above the first conductive structure and in contact with the central portion of the first conductive structure; a channel film disposed above a portion of the ferroelectric layer; a second conductive structure disposed above and in contact with the channel film; and a third conductive structure disposed above and in contact with the channel film.