3D NAND Stair-Step Wordline Layout With Fewer Masking Steps
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Solution Overview
Problem
Current memory circuitry technologies face challenges in efficiently forming vertically-stacked memory cells with precise electrical coupling and structural integrity, particularly in the stair-step structure of NAND architecture, which affects the reliability and access to wordlines in memory arrays.
Innovation Solution
The method involves forming a stack with vertically-alternating conductive and insulative tiers, creating channel openings that directly couple with the conductor tier, and using a stair-step structure with alternating spacers and etching steps to form multiple treads in the stairs, enabling direct electrical access to wordlines and enhancing the structural integrity of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional masking steps are used to form stair-step structures, then precise electrical coupling can be achieved, but the manufacturing complexity and number of steps increase
Solution Approach 1:
The patent extracts and removes the complex masking steps from the conventional fabrication process. By using a direct etching approach on the stack structure, the method eliminates the need for multiple masking layers and alignment steps, thereby reducing manufacturing complexity while maintaining the precision of electrical coupling between wordlines and bitlines.
Solution Approach 2:
The patent replaces the mechanical masking system (photolithography masks, alignment mechanisms) with a direct etching system. This substitution eliminates the mechanical complexity of mask alignment and application, while achieving the same electrical coupling precision through controlled etching of the stair-step structure.
2Adaptability or versatility
If multiple stair-step structures are used to access wordlines, then comprehensive electrical access is achieved, but the structural complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges multiple stair-step structures into a unified, integrated structure. By forming all wordline contacts through a single etching process that creates interconnected steps, the design reduces the number of separate structures needed while maintaining comprehensive electrical access to all wordlines in the memory array.
Solution Approach 2:
The unified stair-step structure serves multiple functions simultaneously: it provides electrical access to multiple wordlines, maintains structural integrity across the memory array, and enables scalable expansion. This multi-functional design eliminates the need for separate specialized structures for each wordline access.
3Productivity
If vertically-stacked memory cells are formed with precise electrical coupling, then memory density increases, but the structural integrity and reliability may be compromised
Solution Approach 1:
The patent applies local quality optimization by designing the stair-step structure with varying geometries at different locations. The steps are configured with specific widths, depths, and spacing tailored to local electrical and mechanical requirements, ensuring both precise electrical coupling for high density and adequate structural support for reliability in vertically-stacked cells.
Data Source
AI summary
Memory circuitry comprising strings of memory cells comprises a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers in a memory-array region. The insulative tiers and the conductive tiers extend from the memory-array region into a stair-step region. The stair-step region comprises a cavity comprising a flight of stairs extending along a first direction. Multiple different-depth and height-sequential treads in individual of the stairs extend along a second direction that is orthogonal to the first direction. Individual of the multiple different-depth treads comprise conducting material of one of the conductive tiers. The cavity comprises a pair of laterally-opposing outermost sidewalls relative to the second direction and that individually extend along the first direction. The multiple different-depth and height-sequential treads in the individual stairs comprise a single flight of said treads that extends along the second direction from one of the laterally-opposing outermost sidewalls to the other of the laterally-opposing outermost sidewalls. Methods are disclosed.