Storage Capacitor Structure Using Insulation Posts for Node Scaling

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Solution Overview

Problem

The increasing depth-to-width ratio of capacitor holes in semiconductor memory structures complicates manufacturing and makes it difficult to control precision sizes, leading to incompact filling and adverse electrical properties.

Innovation Solution

A semiconductor structure with an array area and a circuit area, featuring storage capacitor units composed of insulation posts, a bottom electrode layer covering the posts, a top electrode layer facing the bottom electrode, and a capacitor dielectric layer, where one electrode layer is continuous and the other is discrete, facilitating increased facing area and improved electrical properties.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the capacitor hole depth-to-width ratio is increased to maintain storage capacity as process node reduces, then storage capacity is preserved, but manufacturing process difficulty increases and precision control deteriorates

Engineering Contradiction:
Improvestorage capacityVSAvoidcapacitor hole precision size control
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The capacitor structure is segmented into multiple components: insulation posts arranged in an array, discrete film layers for electrodes, and a continuous film layer. This segmentation replaces the traditional single capacitor hole structure with a distributed array of insulation posts, enabling easier manufacturing while maintaining storage capacity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from a vertical capacitor hole structure (single dimension) to a planar array of insulation posts with discrete film layers (multiple dimensions). The insulation posts are distributed in both first and second directions, creating a two-dimensional arrangement that increases storage capacity without requiring deep holes.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If traditional cup or columnar vertical stacked capacitor structures are used, then manufacturing is simpler, but electrical properties deteriorate due to incompact filling at reduced process nodes

Engineering Contradiction:
Improvecapacitor structure manufacturingVSAvoidelectrical properties
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

Different regions of the capacitor structure have different properties: the insulation posts provide localized dielectric support, the discrete film layers provide electrode functionality, and the continuous film layer provides overall structural integrity. This local differentiation enables compact filling and improved electrical properties while maintaining ease of manufacture.

Inventive Principle:
Principle #3Local quality

3Quantity of substance

If capacitor hole size is reduced to increase storage density, then storage density improves, but process difficulty and precision control worsen

Engineering Contradiction:
Improvestorage densityVSAvoidprocess difficulty
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Multiple insulation posts are merged into a single capacitor unit, with discrete film layers covering multiple posts simultaneously. This merging approach increases storage density by utilizing multiple posts per capacitor while avoiding the need to manufacture individually smaller capacitor holes, thus reducing process difficulty.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12120863B2Semiconductor structure and manufacturing method thereof
Publication Date: 2024.10.15 CHANGXIN MEMORY TECH INC
  • US12120863B2 patent drawing
  • US12120863B2 patent drawing
  • US12120863B2 patent drawing

AI summary

A semiconductor structure includes a substrate, a storage capacitor unit, a transistor, and an electrical connection structure. The storage capacitor unit is located at an array area and includes: N insulation posts, distributed in a direction parallel to a surface of the substrate; a bottom electrode layer; a top electrode layer, directly facing the bottom electrode layer; and a capacitor dielectric layer, located between the top and bottom electrode layers. One of the bottom or top electrode layers corresponding to the N insulation posts is a continuous film layer, and the other is discrete film layers. The transistor is located at a circuit area and includes a capacitor control terminal located in the substrate of the circuit area. The electrical connection structure is electrically connected to the capacitor control terminal, and extends from the circuit area to the array area to come into contact with a corresponding discrete film layer.