Dual-Port SRAM Ground-Line Segmentation for Balanced Ground Bounce
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Solution Overview
Problem
Dual port SRAM memory cells experience unbalanced ground bounce due to differences in current during read operations, affecting the write port's performance.
Innovation Solution
The memory cell design includes a write port with two cross-coupled inverters and separate local interconnect lines for the read and write ports, ensuring that current from read operations does not impact the write port, thereby balancing ground bounce.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate local interconnect lines are used for read and write ports, then ground bounce balance is improved, but device complexity increases
Solution Approach 1:
The patent divides the interconnect structure into separate local interconnect lines for the read port and write port. Specifically, the read port has its own local interconnect line connected to the power source signal line, and the write port has separate local interconnect lines, preventing current from one port from affecting the other and thus balancing ground bounce.
2Device complexity
If read and write ports share common interconnect lines, then device complexity is reduced, but ground bounce becomes unbalanced
Solution Approach 1:
The patent divides the interconnect structure into separate local interconnect lines for the read port and write port. Specifically, the read port has its own local interconnect line connected to the power source signal line, and the write port has separate local interconnect lines, preventing current from one port from affecting the other and thus balancing ground bounce.
Data Source
AI summary
A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.