Top-Gate Array Substrate with Integrated Light Shielding
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Solution Overview
Problem
Oxide-based thin film transistors with a top-gate structure face challenges in design due to susceptibility to light, requiring a light shielding layer and complex hole etching processes, which complicates the manufacturing of backplates and increases the risk of defects.
Innovation Solution
An array substrate is designed with a light shielding layer, a buffer layer to insulate and shield the active layer, and a patterned electrode layer with via-holes for electrical connections, simplifying the etching process and reducing the risk of defects by providing a stable bonding and preventing light exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a light shielding layer is added to protect the top-gate structure from light, then the electrical characteristics are improved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent combines the light shielding layer and gate electrode into a single integrated structure. The gate electrode serves dual functions: as the control electrode for the transistor and as the light shielding layer protecting the active layer from light exposure. This merging eliminates the need for a separate light shielding layer, thus improving electrical characteristics while reducing device complexity.
Solution Approach 2:
The gate electrode is designed to perform multiple functions simultaneously: electrical control of the transistor channel and optical shielding of the active layer. By making the gate electrode multi-functional, the patent avoids adding extra components, thereby improving reliability without increasing device complexity.
2Reliability
If a double channel structure with upper and lower channels is used to improve electrical characteristics, then the performance is improved, but the manufacturing process becomes more complicated and defect risk increases
Solution Approach 1:
The patent extracts and eliminates the lower channel structure, retaining only the upper channel formed by the top-gate configuration. This simplification removes the complexity of creating and maintaining two separate channels while preserving the essential electrical characteristics through the single upper channel controlled by the gate electrode.
Solution Approach 2:
Instead of using a conventional bottom-gate structure with light coming from below, the patent inverts the gate position to top-gate configuration. This inversion, combined with the gate serving as light shield, simplifies the manufacturing process by eliminating the need for complex dual-channel etching while maintaining electrical performance.
Data Source
AI summary
An array substrate and a manufacturing method thereof, a display panel and display device relating to display technology are provided. The array substrate includes: a substrate; a light shielding layer being of electrical conductive over the substrate; a buffer layer over the light shielding layer; an active layer insulated from the light shielding layer by the buffer layer and shielded by the light shielding layer against light radiation; a gate insulating layer disposed over the active layer; and a patterned first electrode layer having a first electrode over the gate insulating layer, the first electrode being a gate electrode; wherein the patterned first electrode layer further comprises a second electrode over the buffer layer, the second electrode having at least a portion in contact with the buffer layer. The buffer layer comprises a first via-hole, and the second electrode is in electrical connection with the light shielding layer through the first via-hole.