Stacked Backside-Illuminated QIS for Cluster-Parallel Readout
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Solution Overview
Problem
Conventional image sensor technologies face challenges in realizing sub-micron pitch jots with high conversion gain and low noise for low bit-error-rate signals, implementing high-speed and low-power readout circuits for large jot arrays, and efficiently transferring high data rates from QIS cameras.
Innovation Solution
A stacked Quanta Image Sensor (QIS) architecture with vertically stacked layers and conductive interconnections between adjacent layers, featuring separate substrates for jot arrays and readout circuitry, and integrated image processing to reduce parasitic capacitance and power consumption, enabling high-speed data transfer and low-power operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional single-layer image sensor architecture is used, then device complexity is low, but bandwidth is limited and power consumption is high
Solution Approach 1:
The patent transitions from a conventional planar single-layer architecture to a three-dimensional stacked architecture with multiple layers connected via through-silicon vias (TSVs). This vertical stacking enables parallel signal paths and increases bandwidth without proportionally increasing device complexity, as the third dimension provides additional routing and processing capacity.
Solution Approach 2:
The image sensor is divided into multiple functional layers: photodetector layer, readout circuit layer, and processing layer. Each layer performs specific functions independently, allowing optimized signal processing at each stage and enabling higher bandwidth through parallel operations across layers while managing complexity through functional separation.
2Productivity
If high-speed readout circuits are implemented, then productivity increases, but power consumption increases
Solution Approach 1:
Signal processing operations are performed in advance at intermediate stages within the stacked architecture. Readout circuits in the middle layer perform initial signal conditioning and filtering before signals reach the final processing layer, reducing the computational burden and power consumption of high-speed operations while maintaining high frame rates.
Solution Approach 2:
The intermediate readout circuit layer acts as an intermediary between the photodetector layer and the final processing layer. This intermediary performs signal amplification, filtering, and preliminary processing, reducing the data volume and complexity that must be processed at full speed in the final layer, thereby lowering overall power consumption while maintaining high productivity.
3Measurement precision
If sub-micron pitch jots are implemented, then measurement precision increases, but noise increases
Solution Approach 1:
The photodetector array is segmented into densely packed sub-micron pitch jots (journalist photodetectors) that individually detect photons. This segmentation enables high spatial resolution while the stacked architecture provides separate processing paths that can filter and correlate signals to reduce noise through spatial and temporal processing.
Solution Approach 2:
The readout circuit layer serves as an intermediary that receives signals from the sub-micron pitch photodetectors and performs noise filtering, signal conditioning, and correlation processing before passing data to the final processing layer. This intermediary processing reduces the impact of noise while preserving the high spatial resolution information.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances bandwidth and reduces power consumption, allowing for thousands of frames per second while maintaining low bit-error rates and efficient data processing, addressing the limitations of conventional image sensor technologies.
Implementation Method 1
a first layer to implement a jot array... vertically stacked layers... conductive interconnections... separate substrates for jot arrays and readout circuitry
Data Source
AI summary
Some embodiments provide a Quanta Image Sensor (QIS) comprising 3D vertically-stacked photosensor array and readout circuitry. In some embodiments, an imaging array comprises a plurality of single-bit or multi-bit jots, and readout circuitry in electrical communication with the imaging array and configured to quantize, for each jot, an analog signal corresponding to the electrical signal of the jot, wherein the imaging system is configured as a 3D vertically integrated circuit with the imaging array stacked vertically above the readout circuitry. The imaging array may be configured as an array of clusters with respect to the readout circuitry, each cluster configured as an array of n by m jots. The imaging array may include a further image processing circuitry layer disposed below the readout circuitry layer. Neighboring layers may be implemented on separate substrates and/or in a common substrate.