Monolithic LED Chip Layout for High Voltage and Low Light Absorption
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional monolithic LED chips face efficiency losses due to light absorption by metal barrier layers, especially when these layers extend beyond the mirror periphery, leading to reduced external quantum efficiency and overall emission dimming effects, particularly pronounced in multi-junction chips.
Innovation Solution
The solution involves patterning barrier layers smaller than the mirror layers to minimize exposure and absorption, with insulating layers surrounding interconnects to prevent Ag migration and using reflective metal layers with high reflectivity to enhance light extraction, while maintaining the integrity of the LED chip's structure and reducing dark spots between active regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If barrier layers extend beyond the mirror periphery to provide electrical connection, then electrical conductivity is improved, but light absorption increases and external quantum efficiency decreases
Solution Approach 1:
The harmful portion of the barrier layer that extends beyond the mirror periphery is removed. The patent specifically patterns the barrier layer to be smaller than the mirror layer, extracting only the necessary portion that provides electrical connection while eliminating the excess that causes light absorption and efficiency loss.
Solution Approach 2:
The barrier layer is selectively positioned only where electrical connection is needed (under or at the edges of the mirror periphery) rather than extending uniformly beyond the mirror. This local placement ensures electrical functionality while minimizing light absorption in the critical emission regions.
2Power
If multiple active regions are arranged in series to increase operating voltage, then power output is improved, but light absorption by interconnect elements increases and overall emission efficiency decreases
Solution Approach 1:
An insulating layer is introduced as an intermediary between the metal interconnect elements and the light emission regions. This insulating layer prevents direct contact between the metal and semiconductor while allowing light to pass through to the active regions, reducing parasitic absorption by the interconnect structure.
Solution Approach 2:
The interconnect elements are positioned in the lateral plane rather than extending vertically through the light emission path. By arranging multiple active regions in series laterally and using planar interconnects with insulating coverage, the design eliminates vertical metal paths that would absorb light, maintaining efficiency while achieving high voltage operation.
3Loss of energy
If reflective metal layers are used to enhance light extraction, then light extraction efficiency is improved, but manufacturing complexity increases due to precise alignment requirements
Solution Approach 1:
The barrier layer and reflective metal layer are merged into a single integrated structure. The barrier layer is positioned to coincide with or be slightly smaller than the mirror layer, combining the electrical connection function and the light reflection function into one aligned structure, thereby simplifying manufacturing while maintaining high reflectivity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly enhances the external quantum efficiency and overall emission characteristics of monolithic LED chips by minimizing light absorption and maintaining high reflectivity, resulting in improved brightness and efficiency, similar to that of single-junction chips, while maintaining the appearance of a continuous light source.
Implementation Method 1
using reflective metal layers with high reflectivity to enhance light extraction
Implementation Method 2
insulating layers surrounding interconnects to prevent Ag migration
Implementation Method 3
patterning barrier layers smaller than the mirror layers to minimize exposure and absorption
Data Source
AI summary
Monolithic LED chips are disclosed comprising a plurality of active regions on a submount, wherein the submount comprises integral electrically conductive interconnect elements in electrical contact with the active regions and electrically connecting at least some of the active regions in series. The submount also comprises an integral insulator element electrically insulating at least some of the interconnect elements and active regions from other elements of the submount. The active regions are mounted in close proximity to one another with at least some of the active regions having a space between adjacent ones of the active regions that is 10 percent or less of the width of one or more of the active regions. The space is substantially not visible when the LED chip is emitting, such that the LED chips emits light similar to a filament.