3D NAND Dual-Deck Transition Layer for Channel Overlap Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 3D NAND memory devices, poor overlap between upper and lower channel structures can lead to enlarged critical dimensions and voids in word line layers, causing electrical leakage or shorts.
Innovation Solution
A dual deck structure with transition layers and a slit structure is introduced, where dielectric and conductive portions are strategically placed between insulating layers to prevent upper channel structures from extending into conductive regions, thereby maintaining proper alignment and preventing electrical issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional stacking of memory cells is used to increase storage capacity, then device density improves, but overlap margin between upper and lower channel structures deteriorates
Solution Approach 1:
The patent divides the channel structure into segmented regions with different critical dimensions. The lower channel structure has a first critical dimension while the upper channel structure has a second critical dimension that is smaller, creating an offset that improves overlap margin. This segmentation allows each region to be optimized independently for its specific function and alignment requirements.
Solution Approach 2:
The patent applies different critical dimensions to different spatial locations of the channel structures. Specifically, the lower channel structure maintains a larger critical dimension for optimal performance, while the upper channel structure uses a smaller critical dimension to accommodate alignment tolerances and improve overlap margin in the stacked configuration.
2Quantity of substance
If critical dimensions are reduced to increase device density, then storage capacity improves, but voids and electrical leakage increase
Solution Approach 1:
Instead of uniformly reducing critical dimensions across all channel structures to increase density, the patent inverts the approach by using different critical dimensions strategically. The upper channel structure uses a smaller critical dimension than the lower one, which prevents void formation and electrical leakage while still achieving increased device density through the stacked architecture.
3Ease of manufacture
If uniform critical dimensions are used in stacked channel structures, then manufacturing simplicity is maintained, but alignment precision deteriorates
Solution Approach 1:
The patent applies different critical dimensions to different channel structures based on their specific alignment requirements. The lower channel structure uses a first critical dimension optimized for its formation process, while the upper channel structure uses a second, smaller critical dimension optimized for alignment with the lower structure, thereby improving overall alignment precision.
Solution Approach 2:
The patent changes the critical dimension parameter between different channel structures in the stack. By adjusting the critical dimension of the upper channel structure to be smaller than that of the lower channel structure, the patent optimizes the alignment precision and overlap margin while maintaining manufacturability through standard fabrication processes.
Data Source
AI summary
A semiconductor device includes a first stack of alternating first word line layers and first insulating layers over a semiconductor layer. The first stack includes a first array region and a first staircase region adjacent to the first array region. The semiconductor device includes a second stack of alternating second word line layers and second insulating layers, where the second stack includes a second array region over the first array region and a second staircase region adjacent to the second array region and over the first staircase region. The first stack further includes a first transition layer over the first word line layers. The first transition layer includes a first dielectric portion in the first array region that surrounds the first channel structure and a first conductive portion. The first transition layer is disposed between two adjacent first insulating layers of the first insulating layers.