Micro LED Epitaxial Structure for Regrowth Interface Neutralization

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Solution Overview

Problem

The reduction in light emission efficiency of micro LED displays due to contamination and the formation of unintended n-type layers during the crystal growth and regrowth process in the production of light emitting elements with sequentially stacked active layers.

Innovation Solution

Incorporating a non-n layer with a group III nitride semiconductor containing O or Si and a p-type impurity between the second active layer and the first p layer, and between the middle layer and the second p layer, to neutralize the regrowth interface and prevent the formation of unintended n-type layers, thereby maintaining light emission efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If the wafer is taken out of the growth furnace to form grooves and then recharged for regrowth, then the groove formation process can be completed, but the wafer becomes contaminated with impurities that form unintended n layers at the regrowth interface, reducing light emission efficiency

Engineering Contradiction:
Improvegroove formation processVSAvoidlight emission efficiency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A non-n layer is introduced as an intermediary layer between the regrown semiconductor layer and the active layer. This non-n layer acts as a mediator that prevents direct contact between the impurity-contaminated regrowth interface and the active layer, thereby blocking the formation of unintended n-type regions that would reduce light emission efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts and isolates the problematic regrowth interface from the active layer by removing a portion of the active layer to form a groove, then filling it with a non-n layer. This separation extracts the impurity source (regrowth interface) from the light-emitting region, preventing contamination from affecting light emission efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

2Adaptability or versatility

If three active layers are sequentially stacked on the same substrate to achieve full-color emission, then color display capability is improved, but the manufacturing process becomes more complex requiring multiple growth cycles and groove formation steps

Engineering Contradiction:
Improvefull-color emission capabilityVSAvoidmanufacturing process complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the active layer into multiple sections, with portions removed to form grooves at specific positions. This segmentation allows different active layers to be selectively exposed and connected to different electrode patterns, enabling full-color emission while maintaining manageable manufacturing complexity through structured division.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a vertical dimension by forming grooves that extend into the active layer, creating a three-dimensional structure with exposed side surfaces. This dimensional change allows for selective electrical connection of different active layers through vertical electrodes, achieving full-color capability without proportionally increasing horizontal process complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240313034A1Light emitting element and production method therefor
Publication Date: 2024.09.19 TOYODA GOSEI CO LTD
  • US20240313034A1 patent drawing
  • US20240313034A1 patent drawing
  • US20240313034A1 patent drawing

AI summary

A light emitting element includes: a substrate; an n layer provided over the substrate as defined herein; a first active layer provided over the n layer as defined herein; a middle layer provided over the first active layer as defined herein; a second active layer provided over the middle layer as defined herein; a groove having a depth reaching the middle layer from a side of the second active layer; a first p layer provided over the second active layer as defined herein; and a second p layer provided over the middle layer exposed on a bottom surface of the groove as defined herein, and a non-n layer including a group III nitride semiconductor and containing O or Si and a p-type impurity is provided between the second active layer and the first p layer and between the middle layer and the second p layer.