Self-Aligned Vertical Solid-State Fabrication for Precise Substrate Bonding
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Solution Overview
Problem
The existing methods for fabricating vertical solid state devices, such as LEDs, are complex and costly, requiring multiple photolithography steps with high chances of inaccuracies, and face challenges in aligning and hermetically bonding substrates due to size and thermal expansion differences, leading to reduced yields and performance issues.
Innovation Solution
A self-aligned fabrication process that simplifies photolithography by using a single lithography step, depositing device layers with ohmic contact layers, and selectively etching to form patterned conductive layers, allowing for precise alignment and hermetically sealed bonding between microdevice substrates and system substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithography steps are used to fabricate microLED devices, then device patterning can be achieved, but manufacturing complexity increases and alignment accuracy decreases
Solution Approach 1:
The patent combines multiple photolithography steps into a single lithography process by using a self-aligned fabrication approach. The method integrates the formation of microLED devices, contact pads, and bonding structures in one unified process flow, eliminating the need for separate masking and alignment steps that traditionally required multiple photolithography cycles.
Solution Approach 2:
The patent employs preliminary structuring where sacrificial layers and self-aligned features are formed before final device definition. The self-aligned contact pads and bonding structures are pre-positioned using the lithography pattern as a reference, ensuring precise alignment without requiring subsequent realignment operations.
2Reliability
If wafer substrate and system substrate are bonded together, then device integration is achieved, but alignment difficulty increases due to size and thermal expansion differences
Solution Approach 1:
The patent changes the bonding parameters by performing bonding at elevated temperatures that facilitate thermal expansion matching between substrates. The process utilizes controlled thermal conditions to accommodate differences in thermal expansion coefficients, enabling reliable bonding despite material mismatches between wafer and system substrates.
Solution Approach 2:
The patent introduces an intermediary bonding layer or interface structure that mediates between the wafer substrate and system substrate. This intermediate layer compensates for dimensional mismatches and thermal expansion differences, facilitating alignment and bonding while protecting against stress and deformation.
3Reliability
If hermetic sealing is implemented between substrates, then device protection is improved, but process complexity and difficulty increase
Solution Approach 1:
The patent merges the hermetic sealing function with the bonding process itself. The same bonding steps that join the substrates together also create the hermetic seal, eliminating the need for separate sealing operations. The bonding interface is designed to provide both mechanical attachment and environmental protection simultaneously.
Solution Approach 2:
The bonding structure and process are designed to serve multiple functions: mechanical attachment, electrical connection, and hermetic sealing. The same bonding layer and process conditions achieve all three objectives, reducing overall process complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances production yield, reduces fabrication costs, and ensures accurate alignment and reliable, bubble-free bonding, improving the performance and efficiency of vertical solid state devices.
Implementation Method 1
depositing an ohmic contact layer on an upper surface of one of the plurality of device layers
Implementation Method 2
selectively etching down the doped conductive layer that does not substantially etch the active layer
Implementation Method 3
bonding the microdevices to the system substrate
Data Source
AI summary
Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.