Pixel Unit Structure With 3D TFT Channel for Higher Aperture Ratio

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Solution Overview

Problem

LCD display panels face a challenge in achieving high pixel aperture ratio while maintaining high resolution, as increased metal wires reduce the pixel aperture ratio, limiting light efficiency and display performance.

Innovation Solution

A pixel unit structure is designed with a thin film transistor that includes a semiconductor portion covering a protrusion of the gate insulating layer, allowing the gate line to serve as a light shield, eliminating the need for light shielding strips and increasing the channel length, thereby enhancing the aperture ratio and stability of the thin film transistor.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the resolution of LCD display is increased, then the display quality is improved, but the pixel aperture ratio decreases due to more metal wires

Engineering Contradiction:
Improvedisplay resolutionVSAvoidpixel aperture ratio
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The gate line is merged with the light shielding function by extending it to cover the pixel region, eliminating the need for separate light shielding strips. This integration allows the gate line to serve dual purposes: electrical control and optical shielding, thereby increasing the pixel aperture ratio while maintaining high resolution

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate line is designed to perform multiple functions simultaneously: it acts as both the control electrode for the thin film transistor and as the light shielding structure. This multi-functionality reduces the number of separate components needed, increasing the light passing area while maintaining display resolution

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If the pixel aperture ratio is increased to improve light efficiency, then the light passing efficiency is improved, but the channel length of the thin film transistor decreases

Engineering Contradiction:
Improvelight passing efficiencyVSAvoidchannel length
Core Design Contradiction:
Use of energy by moving objectVSLength of moving object

Solution Approach 1:

The semiconductor layer is extended in the vertical dimension to cover the protrusion of the gate insulating layer, creating a three-dimensional channel structure. This allows the channel length to be increased along the vertical direction while maintaining a compact horizontal footprint, thus preserving light efficiency

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The semiconductor layer is nested over the gate insulating layer protrusion, creating a stacked configuration where the channel extends vertically above the gate structure. This nesting approach increases the channel length without occupying additional horizontal space, maintaining the pixel aperture ratio

Inventive Principle:
Principle #7Nested doll (Nesting)

3Reliability

If the channel length is increased to improve transistor stability, then the transistor stability is improved, but the pixel aperture ratio decreases

Engineering Contradiction:
Improvetransistor stabilityVSAvoidpixel aperture ratio
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The channel length is extended in the vertical dimension by having the semiconductor layer cover the protrusion of the gate insulating layer. This three-dimensional channel configuration increases the channel length for improved transistor stability while maintaining a compact horizontal footprint that preserves the pixel aperture ratio

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240304633A1Pixel Unit Structure and Preparation Method thereof, Display Panel and Preparation Method Thereof
Publication Date: 2024.09.12 BOE TECHNOLOGY GROUP CO LTD
  • US20240304633A1 patent drawing
  • US20240304633A1 patent drawing
  • US20240304633A1 patent drawing

AI summary

The present invention provides a pixel unit structure, in which a source electrode is connected to a data line in a thin film transistor; the gate electrode is connected to the gate line; the drain electrode is disposed on a side of the gate insulating layer away from the substrate; the metal oxide semiconductor layer is disposed on a side of the gate insulating layer away from the substrate, and includes a semiconductor portion and a first conductive portion and a second conductive portion respectively located on both sides of the semiconductor portion; a terminal of the first conductive portion adjacent to the drain electrode is connected to the drain electrode or serves as at least a portion of the drain electrode; and the second conductive portion is connected to the source electrode through a first via formed correspondingly on the gate insulating layer and the interlayer dielectric layer.