Vertical Ferroelectric Memory Channel Using Oxide 2-DEG to Cut Interface Traps
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing data storage capacity and endurance due to interfacial layers between ferroelectric and semiconductor layers, which lead to interface traps and degraded performance.
Innovation Solution
The semiconductor memory device incorporates a semiconductor layer with an oxide 2-dimensional electron gas (2-DEG) layer as a channel region, featuring an n-type channel layer with an interfacial layer containing oxygen vacancies between oxide layers, enhancing contact resistance and reducing interface traps, and utilizing a TiO2/Al2O3 heterostructure for high-k film formation to support low voltage operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional polysilicon-based channel layers are used with ferroelectric gate dielectric layers, then the device structure is simple and manufacturing is easier, but interface traps form at the ferroelectric-semiconductor interface leading to degraded performance and reduced endurance
Solution Approach 1:
The patent employs a composite oxide semiconductor layer structure consisting of multiple oxide layers (e.g., InGaO3, InO3, Ga2O3) with different compositions and properties. This composite structure creates an oxide 2-DEG channel that reduces interface traps between the ferroelectric gate dielectric and channel, thereby improving endurance while managing the increased structural complexity through systematic material composition design
Solution Approach 2:
The patent modifies the channel layer by creating oxygen vacancies through controlled reduction processes (e.g., forming gas annealing, plasma treatment). This parameter change transforms the oxide semiconductor from a stoichiometric state to a reduced state with oxygen deficiencies, which generates the oxide 2-DEG and significantly reduces interface traps, improving reliability without requiring fundamentally new materials
2Use of energy by moving object
If high-k ferroelectric gate dielectric layers are used to enable low voltage operations, then power consumption is reduced, but interface traps form at the ferroelectric-semiconductor interface degrading device performance
Solution Approach 1:
The patent uses a composite oxide semiconductor channel layer that is specifically engineered to interface with high-k ferroelectric gate dielectrics. The multi-layer oxide structure (combining elements like In, Ga, Sn, Zn) provides a gradient composition that minimizes interface mismatch and trap formation, allowing the device to operate at low voltages while maintaining high performance
Solution Approach 2:
The patent creates localized regions with different oxide compositions and oxygen vacancy concentrations within the channel layer. The interface region adjacent to the ferroelectric gate dielectric is specifically engineered with optimal oxygen vacancy density to minimize traps, while bulk regions maintain different properties for optimal carrier transport, achieving both low power operation and high performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the endurance and performance of semiconductor memory devices by reducing interface traps and enabling low voltage operations, providing improved characteristics compared to traditional polysilicon-based channel layers.
Implementation Method 1
the n-type channel layer includes an oxide 2-dimensional electron gas (2-DEG) layer extending in the vertical direction
Implementation Method 2
the interfacial layer including an oxygen vacancy between the first oxide layer and the second oxide layer
Implementation Method 3
utilizing a TiO2/Al2O3 heterostructure for high-k film formation to support low voltage operations
Implementation Method 4
TiO2/Al2O3 heterostructure for high-k film formation
Data Source
AI summary
A semiconductor memory device having improved characteristics may be provided. The semiconductor memory device includes a cell substrate, a plurality of gate electrodes sequentially stacked on the cell substrate, a semiconductor layer extending in a vertical direction, intersecting an upper side of the cell substrate, and intersecting the plurality of gate electrodes, and a gate dielectric layer including ferroelectrics between each of the gate electrodes and the semiconductor layer, wherein the semiconductor layer includes an n-type channel layer and a p-type channel layer each extending in the vertical direction, and the n-type channel layer includes an oxide 2-dimensional electron gas (2-DEG) layer extending in the vertical direction.