Porous Semiconductor Isolation for Low-Leakage RF Switches
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Solution Overview
Problem
Bulk semiconductor substrates with high resistivity polycrystalline isolation layers exhibit higher harmonics and substrate leakage current compared to semiconductor-on-insulator (SOI) substrates, which are not cost-effective and have inferior performance characteristics for radio frequency (RF) devices.
Innovation Solution
An integrated circuit (IC) structure is developed using a bulk semiconductor substrate with a trench isolation, a dielectric layer, and a porous semiconductor layer extending through a polycrystalline isolation layer, providing improved electrical isolation and performance characteristics similar to or exceeding those of SOI substrates at a lower cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistivity polycrystalline isolation layer is used in bulk semiconductor substrates, then additional isolation to devices is provided, but harmonics and substrate leakage current increase
Solution Approach 1:
The patent introduces a porous semiconductor layer (e.g., porous silicon) adjacent to the trench isolation structure. This porous layer provides trap states that capture charge carriers, thereby reducing substrate leakage current and harmonics while maintaining device isolation. The porous structure creates a depletion region that acts as an additional isolation mechanism without the harmful effects of high resistivity polycrystalline layers.
Solution Approach 2:
The patent applies different material properties to different regions: the porous semiconductor layer is localized adjacent to the trench isolation where isolation is most needed, while the bulk substrate maintains its original properties. This localized approach provides enhanced isolation functionality only where required, avoiding the need for high resistivity polycrystalline layers across the entire substrate.
2Reliability
If SOI substrate with polycrystalline isolation layer is used, then device isolation is improved, but cost increases and performance is inferior for RF devices
Solution Approach 1:
The patent changes the electrical parameters of the bulk semiconductor substrate by introducing a porous layer with controlled porosity (e.g., 30-70% void space). This creates a region with effective high resistivity and trap density without requiring a complete SOI structure. The porous layer's electrical properties can be tuned by controlling formation parameters such as electrochemical etching conditions, achieving SOI-like isolation performance on cost-effective bulk substrates.
Solution Approach 2:
The patent creates a composite structure combining the bulk semiconductor substrate with a porous semiconductor layer. This composite provides the benefits of SOI substrates (low leakage, good RF performance) while maintaining the cost advantages of bulk substrates. The porous layer acts as an intermediate structure with properties between crystalline semiconductor and insulator.
3Reliability
If trench isolation is used to isolate active devices, then lateral isolation is achieved, but additional isolation layers are needed to reduce harmonics and parasitic losses
Solution Approach 1:
The patent merges the trench isolation structure with the porous semiconductor layer formation into a single integrated isolation system. The porous layer is formed adjacent to the trench isolation in the same processing sequence, creating a unified isolation architecture that provides both lateral isolation (trench) and vertical/substrate isolation (porous layer) functions simultaneously, reducing the need for separate isolation layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The IC structure achieves better current leakage, harmonic distortion, cross-talk resistance, effective resistivity, permittivity, and attenuation compared to SOI substrate devices, while using a lower cost, low resistivity bulk semiconductor substrate, reducing leakage current and enhancing overall RF device performance.
Implementation Method 1
a porous semiconductor layer under the dielectric layer in a bulk semiconductor substrate adjacent a trench isolation
Data Source
AI summary
An integrated circuit (IC) structure, a switch and related method, are disclosed. The IC structure includes an active device, e.g., a switch, over a bulk semiconductor substrate, and an isolation structure under the active device in the bulk semiconductor substrate. The isolation structure may include a trench isolation adjacent the active device in the bulk semiconductor substrate, a dielectric layer laterally adjacent the trench isolation and over the active device, and a porous semiconductor layer in the bulk semiconductor substrate under the dielectric layer laterally adjacent the trench isolation. The IC structure employs a lower cost, low resistivity bulk semiconductor substrate rather than a semiconductor-on-insulator (SOI) substrate, yet it has better performance characteristics for RF switches than an SOI substrate.