Memory Staircase Contacts With Strapping to Prevent Tier Collapse
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Solution Overview
Problem
Vertical memory array architectures in microelectronic devices face challenges such as tier collapse during processing and increased parasitic capacitance due to decreasing feature dimensions, which affect memory density and reliability.
Innovation Solution
The formation of conductive contacts that extend entirely through the vertical extent of the preliminary stack structure, terminating at a single location, and the use of strapping structures to provide electrical connections and structural support, reducing the risk of tier collapse and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the height of the stacks is increased to provide additional memory density, then the memory density is improved, but the stacks become prone to toppling or collapse during processing
Solution Approach 1:
The patent introduces intermediary support structures (sacrificial spacers) between the tiers of the conductive stack structure. These support structures分段 the tall stack into smaller segments, with each segment being mechanically supported by the intermediary elements. This segmentation prevents the entire stack from toppling as a single unit, thereby maintaining stack stability while preserving the increased memory density achieved through additional tiers.
2Quantity of substance
If the dimensions and spacing of conductive features are decreased to increase memory density, then the memory density is improved, but the parasitic capacitance between adjacent conductive features increases
Solution Approach 1:
The patent introduces intermediary insulative structures (dielectric materials) between adjacent conductive features and tiers. These intermediary insulative structures act as mediators that electrically isolate the closely spaced conductive elements. By placing these insulative layers between conductive features, the parasitic capacitance is reduced despite the decreased spacing, thereby maintaining high memory density while mitigating the harmful capacitive effects.
3Quantity of substance
If additional tiers of conductive structures are formed to increase memory density, then the memory density is improved, but the complexity of the staircase structures and processing increases
Solution Approach 1:
The patent employs preliminary formation of sacrificial spacer structures and insulative layers before constructing the conductive tiers. These preliminary structures are prepared in advance to provide mechanical support and electrical isolation during subsequent processing steps. By performing these preparatory actions beforehand, the patent simplifies the overall manufacturing process for high-tier stacks, reducing the complexity that would otherwise arise from attempting to assemble and support tall stacks without pre-positioned support elements.
Data Source
AI summary
A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprises a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, conductive contacts within a horizontal area of the staircase structure and vertically extending through the stack structure to the source tier, and strapping structures laterally adjacent to the conductive contacts and having upper surfaces substantially coplanar with upper surfaces of the conductive contacts. Each of the strapping structures are in contact with one of the conductive contacts and with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.