Semiconductor Power Line Layout for Stable Local Logic Supply
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Solution Overview
Problem
The existing semiconductor structures face challenges in achieving stable local power supply for high-speed transistors, leading to poor stability of delay time due to high transistor noise and increased resistance in the power supply network, which is exacerbated by the need for strict power supply requirements and limited layout tracks.
Innovation Solution
The semiconductor structure integrates a switch driving device and logic device within a standard cell, with power lines arranged in parallel on the same wiring layer, reducing the resistance value of the local power supply network by eliminating unnecessary interconnection vias and optimizing the layout to improve power supply stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power lines are arranged on different wiring layers with multiple interconnection vias, then connectivity is achieved, but resistance increases and power supply stability deteriorates
Solution Approach 1:
The patent transitions from vertical interconnection via multiple wiring layers to horizontal interconnection on the same wiring layer. Power lines are arranged in parallel on the same layer, extending in the first direction, eliminating the need for vias and reducing resistance while maintaining connectivity.
Solution Approach 2:
The patent removes interconnection vias from the power supply network by reconfiguring the layout. The switch driving device output line directly connects to the logic device power line on the same wiring layer, extracting the harmful via elements that caused high resistance and instability.
2Productivity
If switch driving device and logic device are separated into different standard cells, then device functionality is maintained, but layout space is wasted and integration is reduced
Solution Approach 1:
The patent merges the switch driving device and logic device into a single standard cell layout. The switch driving device is positioned adjacent to the logic device with direct horizontal connection, consolidating previously separate components to improve layout density and integration without increasing structural complexity.
3Ease of manufacture
If multiple interconnection vias are used to connect power lines, then connectivity is achieved, but layout space is occupied and manufacturing complexity increases
Solution Approach 1:
The patent resolves the space occupation issue by changing from vertical via-based connection to horizontal in-plane connection. Power lines extend horizontally on the same wiring layer, eliminating via structures and reducing layout space requirements while simplifying manufacturing processes.
Data Source
AI summary
A semiconductor structure includes: a logic device including a first power line and a second power line located on a same wiring layer, extending along a first direction and arranged in parallel along a second direction, the first direction and the second direction intersecting with each other and being parallel to a plane where the wiring layer is located; and a switch driving device, the switch driving device and the logic device being arranged in parallel along the first direction, the switch driving device including a first input line and a first output line located on the same wiring layer as the first power line, extending along the first direction and arranged in parallel along the second direction, the first output line being connected with the first power line or the second power line.