3D Memory Inter-Select-Gate Electrode Isolation
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in efficiently integrating inter-select-gate electrodes without electrical connection to drain-select-level electrodes, which affects the structural integrity and operational efficiency of the memory stack structures.
Innovation Solution
A method of forming a three-dimensional memory device involving an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers over a substrate, with inter-select-gate electrodes placed between neighboring drain-select-level electrodes, and inter-select-gate dielectrics between these electrodes and drain-select-level electrodes, ensuring they remain electrically disconnected.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If inter-select-gate electrodes are integrated into the memory device, then the operational efficiency and programming capability are improved, but the structural complexity and manufacturing difficulty increase
Solution Approach 1:
The memory device is segmented into distinct functional regions with inter-select-gate electrodes positioned between drain-select-level electrodes. This segmentation allows independent control of different memory string groups, improving operational efficiency while maintaining manageable structural complexity through modular organization.
Solution Approach 2:
The inter-select-gate electrodes are integrated in the vertical dimension between existing drain-select-level electrodes, utilizing the third dimension for electrode placement. This vertical integration adds functionality without significantly increasing lateral footprint, thereby improving operational capability while controlling overall device complexity.
2Ease of manufacture
If inter-select-gate electrodes are electrically connected to drain-select-level electrodes, then the manufacturing process is simplified, but the electrical isolation and operational control are compromised
Solution Approach 1:
An inter-select-gate dielectric layer is introduced as an intermediary between the inter-select-gate electrodes and drain-select-level electrodes. This dielectric layer provides electrical isolation while allowing the electrodes to be formed using compatible manufacturing processes, thus maintaining ease of manufacture while ensuring reliable electrical isolation for proper operational control.
3Manufacturing precision
If inter-select-gate dielectrics are added for electrical isolation, then the electrical control precision is improved, but the manufacturing steps and process complexity increase
Solution Approach 1:
The formation of inter-select-gate dielectrics is merged with existing dielectric deposition steps in the manufacturing process. By combining the isolation layer formation with routine dielectric processing, electrical control precision is improved while minimizing the increase in overall process complexity through integrated fabrication steps.
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.