3D Memory Isolation Structure Layout for Dense Word Line Arrays
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in efficiently forming isolation structures and word lines, which affect the integration and performance of memory elements.
Innovation Solution
A method involving the formation of an alternating stack of insulating and dielectric layers, followed by selective etching to create laterally-extending cavities and filling these with conductive materials to form word lines and dielectric isolation structures, thereby creating a three-dimensional array of memory elements and semiconductor channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional methods are used to form isolation structures and word lines in three-dimensional memory devices, then the manufacturing process is simpler, but the integration density and performance of memory elements are reduced
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming alternating insulating and dielectric layers, creating memory openings through selective etching, forming word lines in cavities, and creating isolation structures. This segmentation enables higher integration density by allowing precise control of each component's formation while maintaining manufacturability through systematic process steps.
Solution Approach 2:
The patent transitions from planar two-dimensional memory structures to three-dimensional vertical structures by stacking alternating insulating and dielectric layers and forming vertical memory openings and word lines. This dimensional change increases integration density by utilizing the vertical dimension for stacking multiple memory elements and word lines.
2Reliability
If alternating stacks of insulating and dielectric layers are formed with selective etching to create word lines and isolation structures, then conductivity and isolation are improved, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies local quality by using different materials (insulating vs. dielectric layers) with distinct etch selectivities in different regions of the alternating stack. This enables selective formation of word lines in cavities and isolation structures in other regions, improving conductivity and isolation performance while managing manufacturing complexity through material-specific processing.
Solution Approach 2:
The patent uses dielectric layers as intermediaries between insulating layers, enabling selective etching processes that create cavities for word lines while preserving the overall stack structure. The dielectric layers act as etch stoppers and masks, facilitating precise formation of conductive and isolating structures without requiring complete reconstruction of the stack.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integration and performance of memory elements by providing a structured array with improved conductivity and isolation, leading to efficient operation of three-dimensional memory devices.
Implementation Method 1
laterally recessing the spacer material layers selective to the insulating layers by performing an isotropic etch process that supplies an isotropic etchant through the memory openings to form a plurality of laterally-extending cavities
Data Source
AI summary
A semiconductor structure includes an alternating stack of insulating layers and composite layers, each of the composite layers includes a plurality of electrically conductive word line strips and a plurality of dielectric isolation structures, and each of the insulating layers has an areal overlap with each electrically conductive word line strip and each dielectric isolation structure within the composite layers within a memory array region in a plan view along a vertical direction, rows of memory openings arranged along the first horizontal direction, where each row of memory openings of the rows of memory openings vertically extends through each insulating layer within the alternating stack and one electrically conductive strip for each of the composite layers, and rows of memory opening fill structures located within the rows of memory openings, where each of the memory opening fill structures includes a vertical stack of memory elements and a vertical semiconductor channel.