3D Memory Conductor Layer Profiling for Channel Width Variation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 3D memory devices, the variation in channel hole widths and sacrificial layer thicknesses leads to uneven programming/erase speeds and undesirable erase state coupling, resulting in non-uniform threshold voltage distribution across memory cells, which impairs device performance.
Innovation Solution
The thickness of conductor layers in 3D memory devices is made nominally proportional to the width of the channel structure along the vertical direction, compensating for the impact of channel width variations and improving the uniformity and stability of memory cell performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of conductor layers is made proportional to channel structure width, then uniformity of memory cell performance is improved, but device complexity increases
Solution Approach 1:
The patent applies local quality by making the thickness of conductor layers position-dependent, specifically proportional to the width of the channel structure at each location. This means different regions of the device have different conductor layer thicknesses tailored to local channel width requirements, thereby compensating for width variations and improving overall performance uniformity without requiring complete redesign of the entire device architecture.
2Reliability
If variable thickness conductor layers are implemented, then threshold voltage distribution uniformity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements parameter changes by systematically varying the thickness parameter of conductor layers based on the channel structure width. Instead of using a uniform thickness parameter throughout the device, the thickness is adjusted as a function of position, creating a graded structure that compensates for channel width variations and achieves more uniform threshold voltage distribution across memory cells.
Data Source
AI summary
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of conductor layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of conductor layers is nominally proportional to a width of the channel structure at the same depth.