Solid-State Devices TRIZ Cases

A tunneling barrier layer blocks dark current in a Schottky photodetector, enabling wider visible-to-infrared detection with faster switching.

A DBR resonant cavity with porous apertures and light-blocking gaps boosts micro-LED emission, preserves conductivity, and limits pixel cross-talk.

Limiting substrate depth and adding recombination features cuts minority-carrier dark current, reducing spurious signals and detection delay.

A split lower-pattern layout lets the upper electrode connect only where needed, avoiding mask-induced peeling defects and improving display yield.

A DBR stopband filters side wavelengths from microLED emission to improve color purity, light output, and pixel isolation.

A shared n-well between paired p-wells creates bidirectional SCR-based ESD protection while cutting chip area and limiting leakage.

Porous high-index particles in thin LED sidewalls confine light, cut optical cross-talk, and enable tighter microLED pixel spacing.

Arrayed semiconductor structures with reflective and insulating layers improve light extraction, optical output, and flexibility while lowering voltage.

Electrochemical porosification of InGaN mesas relieves stress, enabling relaxed epitaxy and aligned RGB micro-LED growth on one substrate.

Sequential etching of copper and conductive capping layers improves pattern accuracy, prevents smudging, and strengthens display connections.

A thiophene-carbazole anode buffer layer improves dark current and afterimage behavior in organic imaging elements while supporting sensitivity and pixel scaling.

Placing parallel capacitor units beneath the pad stabilizes power supply while saving chip area and improving film formation quality.

A thin wiring line between adjacent mesas lowers common cathode resistance while preserving light quality and avoiding warping.

Wider bank structures beside blue color resist modules limit lateral light leakage, reducing pixel crosstalk while improving luminance.

A copied reference current stabilizes SPAD recharge current against process and temperature variation, improving dead-time control and photon detection.

A thin-film flip-chip micro-LED mesa structure reduces pick-and-place errors while maximizing light-emitting area and light extraction.

A cavity-layer IR cut filter on a thin glass substrate reduces flare and ghosting while preserving imaging element strength.

Using RGCB pixels with blue and cyan LEDs plus phosphors, this case expands color gamut while easing micro-LED assembly and improving durability.

A sidewall buffer on micro LED chips absorbs transfer impacts, improves bonding accuracy, and helps contain solder or quantum dot layers.

Different organic film heights on the TFT backplane match RGB LED thicknesses to prevent cracking and unbonding during panel bonding.

A protruding contact member shifts transfer force away from fragile bridge members, improving microLED transfer yield and preventing cavity drop.

Series-connected sub-emission layers keep light emission working despite short defects, improving display reliability with quantum-dot color conversion.

Peripheral pad placement on vertically stacked RGB LEDs reduces chip count and pixel area while supporting stable surface mounting.

A dielectric-wrapped floating gate enables direct source contacts between cells, avoiding spacer damage, shorts, and extra etching steps.

Alternating P-plus and N-plus regions in the polysilicon gate form zener protection that clamps ESD and voltage spikes without increasing cell pitch.

A sparse outer LED unit layout offsets epitaxial centrifugal effects, equalizing doping rates and reducing wavelength variation.

3D surface texturing lengthens the light path in silicon imagers, improving infrared absorption, responsivity, and signal quality in thinner wafers.

A segmented outer passivation layout enables outgassing where needed while blocking peripheral residue that can reduce display visibility and reliability.

Metal-oxide nanoparticle ETLs improve charge injection balance in QLED emissive layers, reducing voltage loss and charge accumulation.

A recessed vertical transfer gate pad increases spacing from the floating diffusion region, cutting GIDL, read noise, and image sensor leakage.

An auxiliary insulating layer and over-etching create an undercut separator within the pixel definition layer, cutting OLED display process steps and cost.

Selective light shielding over TFT channel regions cuts illumination leakage current and reduces flicker in high-PPI LCD panels.

Varying sensing line widths in a multilayer touch sensor offsets line-length resistance differences to improve touch detection accuracy.

Angled active regions and vertical transfer gates expand overlap area in dense pixels, preserving image quality and operational reliability.

Vertical trench MIM capacitors use DEDED deposition, cap-layer edge protection, and offset electrodes to raise capacitance while preventing shorts.

A Fresnel zone plate with alternating refractive index regions focuses short-wave infrared light to enable parallax sensing and focus detection.

Differential-length transfer heads enable one-step micro LED pickup and sequential placement, cutting release and cleaning cycle time.

Shared active regions and asymmetric power rails let multi-row standard cells span mixed-height IC rows without grid-fit violations.

Self-aligned silicide electrodes avoid exposure-step errors on bowed growth substrates, cutting micro-LED defects and improving current injection.

Vertically stacked RGB light emitters use a PN junction layer to avoid chip transfer bottlenecks and reduce interference in high-resolution displays.

A strain relaxation layer with an AlGaN protrusion suppresses dislocations, enabling higher In content and better long-wavelength emission efficiency.

A self-aligned contact electrode connects only to the first semiconductor layer, reducing wiring corrosion, shorts, and micro-LED defects.

Alternating CVD low- and high-index optical layers reduces particle dot defects in camera modules while improving coating smoothness and imaging quality.

Preformed holders and adhesive self-align the LED lens on the board, improving optical axis accuracy and light distribution evenness.

Rear-mounted under-display imaging combines multi-unit pixels and signal correction to suppress flare and diffraction artifacts in video calls.

A detection circuit checks stacked substrate connections and reroutes signals to adjacent paths when failures occur, improving sensor reliability.

Same-polarity voltage at both electrode ends keeps LED self-assembly running despite electrode defects, improving transfer yield and repair time.

Active dies act as communication bridges in reconstructed 3DIC stacks, increasing interconnect density while reducing bottom-die size and yield loss.

Embedded connection portions in sub-pixel units detect splicing offsets during LCD exposure, helping prevent dark lines and misalignment.

Segmented transfer gates arranged symmetrically around a floating diffusion region improve light extraction, well potential control, and signal transfer.

An engineered bulk silicon clamping diode gives GaN power transistors avalanche protection while deep trench isolation cuts crosstalk and parasitic inductance.

A split conductive layer links stacked LED and control circuits without side electrodes, improving insulation, bonding, and manufacturing reliability.

Graphene-based buffer and active layers let micro LEDs and TFTs share one array substrate, simplifying fabrication while improving connection stability.

A wafer-based adhesive film holds regularly arranged MicroLEDs for batch transfer, cutting bonding failures and production time.

Peripheral light-blocking structures shield noisy substrate regions while keeping the sensing area open for more accurate TOF depth capture.

A carrier trap under the control electrode lowers carrier density to suppress snapback and overcurrent while preserving IGBT conduction.

Patterned openings in an opaque layer block diffraction from sparse display pixels and wiring, preserving under-display camera image quality.

Shared floating diffusion nodes and separate column-line connections raise image sensor readout efficiency while protecting sensitivity and frame rate.

Hollowed-out first electrode regions improve light transmission to under-display collection portions while preserving electrical connectivity and display performance.

Sequential silicon compound layers with tuned refractive indices improve OLED light efficiency and color life while simplifying deposition.

Light shielding layers fill concave regions between LED cells to block optical interference, improve color reproducibility, and reinforce thin substrates.

An added second semiconductor layer enables full depletion and faster charge transfer in an organic photoelectric layer, cutting kTC noise.

Each LED lamp bead uses its own drive circuit and trigger input, avoiding series signal breakage and simplifying packaging.

Low-energy argon implantation creates high-resistivity inactive regions on bulk wafers, improving switch linearity and harmonics at lower cost.

Surrounding conductivity-type regions isolate adjacent light receiving elements, cutting crosstalk and dark current in dense arrays.

Uniform free-layer thickness with varied MTJ widths enables multiple MRAM types on one IC while balancing thermal stability, response time, and cost.

A separate bottom electrode, reflector, and coupling structure avoid oxide-driven electrical isolation while preserving high reflectivity in micro display pixels.

A dual-electrode top-emitting OLED structure cuts cathode IR-drop to improve brightness uniformity and light extraction in large panels.

A larger central diffuser with smaller peripheral diffusers extends NIR path length in silicon, improving quantum efficiency across incident angles.

A buried insulator enables monolithic III-V and silicon co-integration on one substrate, avoiding complex wafer bonding while improving reliability.

An intermediate chip carries the through-electrodes and rewiring, cutting stacked semiconductor manufacturing cost while preserving multi-chip functionality.

Shrinking Vss and node contacts in one direction increases gate spacing in FinFET SRAM, reducing bridging risk despite gate-end variation.

A fluorene-based polyimide precursor balances heat resistance with low thermal expansion and high transparency for flexible display films.

A reset-channel potential gradient and dual conversion gain transistor cut reset noise and keep image sensor SNR stable across light levels.

Separating photoelectric conversion elements and detection circuits onto different chips cuts dark current noise and improves light reception efficiency.

Two aligned sensor arrays and a selective absorption layer identify wavelength by intensity ratio, reducing color leakage and artifacts.

Dual heat dissipation layers with tuned refractive indices cool the light-emitting element and improve quantum efficiency and light output.

Embedded wiring inside a ceramic substrate shrinks LED footprint, supports denser element placement, and improves direct power delivery.

An interface film between the lower electrode and dielectric boosts DRAM capacitance, promotes crystallization, and helps limit leakage.

Variable conductor layer thickness matched to channel width improves erase coupling and threshold voltage uniformity in 3D memory cells.

Vertical LED sub-unit stacking shrinks pixel footprint and mounting effort while keeping RGB viewing angles and color mixing more consistent.

Selecting receivers, tuning ODT resistance, and training equalizers across shared data lines cuts training time and improves signal integrity.

A peripheral light-shielding film on the bonded glass substrate blocks stray light with higher alignment accuracy, reducing flare and ghosts.

A trench vertical transfer gate with a low-κ dielectric spacer cuts parasitic capacitance and raises conversion gain for better low-light imaging.

Switch-controlled electrode rows equalize common voltage across large display panels, preventing split-screen artifacts from uneven Vcom.

Reference light-sensing elements track deterioration and adjust illumination to preserve fingerprint image gray levels and reduce identification errors.

Positioning the discharge tip on a plateau side slope lowers the required voltage, preventing line damage and display abnormalities.