Floating N and P Bar Regions for CMOS Latch-up Immunity
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Solution Overview
Problem
As CMOS device dimensions are scaled down, latch-up immunity becomes increasingly difficult to achieve without increasing device and circuit area, as existing solutions like guard rings and deep isolation trenches are impractical and require significant layout and connection complexity.
Innovation Solution
Incorporating floating N and P well regions, referred to as N BAR and P BAR, which are coupled together via a low resistance metal connection, rather than to fixed potentials, to enhance latch-up immunity in CMOS structures, thereby simplifying interconnections and reducing area penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard rings or deep isolation trenches are used to improve latch-up immunity, then latch-up immunity is improved, but device area and layout complexity increase significantly
Solution Approach 1:
The patent changes the electrical potential parameter of the intermediate well regions from fixed potential (ground or VDD) to floating potential. This parameter change allows the structure to achieve latch-up immunity through the formation of depletion regions that block parasitic current paths, without requiring the additional area associated with guard rings or deep isolation trenches.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming intermediate well regions at different depths between the N-well and P-well. This vertical stacking approach achieves latch-up protection without increasing the lateral footprint of the device, effectively trading vertical space for horizontal area efficiency.
2Reliability
If guard rings or deep isolation trenches are used to improve latch-up immunity, then latch-up immunity is improved, but layout and connection complexity increase
Solution Approach 1:
The patent merges the latch-up protection function into the existing well structure by introducing intermediate well regions that are formed using the same doping processes as the N-well and P-well. This integration eliminates the need for separate guard ring structures or deep isolation trenches, simplifying both layout and manufacturing processes.
Solution Approach 2:
The floating intermediate well regions automatically form depletion regions that block parasitic current paths when latch-up conditions are attempted. The structure self-regulates by using the applied voltage to create the protective effect, eliminating the need for external control circuits or complex biasing arrangements.
3Productivity
If device dimensions are scaled down, then device density and integration are improved, but latch-up immunity becomes increasingly difficult to achieve
Solution Approach 1:
The patent addresses scaling challenges by moving the latch-up protection mechanism into the vertical dimension through intermediate well regions. This allows maintain latch-up immunity in scaled devices without proportionally increasing lateral dimensions, thus preserving device density while improving reliability.
Solution Approach 2:
The patent changes the electrical characteristics of the well structure by introducing floating potential regions that create strong depletion fields. This parameter change enables effective latch-up protection even in highly scaled devices where traditional lateral protection mechanisms would require excessive area.
Data Source
AI summary
Latch-up of CMOS devices is improved by using a structure having electrically coupled but floating doped regions between the N-channel and P-channel devices. The doped regions desirably lie substantially parallel to the source-drain regions of the devices between the Pwell and Nwell regions in which the source-drain regions are located. A first (“N BAR”) doped region forms a PN junction with the Pwell, spaced apart from a source/drain region in the Pwell, and a second (“P BAR”) doped region forms a PN junction with the Nwell, spaced apart from a source/drain region in the Nwell. A further NP junction lies between the N BAR and P BAR regions. The N BAR and P BAR regions are ohmically coupled, preferably by a low resistance metal conductor, and otherwise floating with respect to the device or circuit reference potentials (e.g., Vss, Vdd).