Semiconductor Gate Structure Silicide Formation Void Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor manufacturing, the narrowing design rules lead to voids between word lines, causing metal to flow into these voids and resulting in stringer problems due to incomplete filling of insulating layers, which are difficult to clean and can remain, leading to increased interconnection resistance.
Innovation Solution
A method is developed to form gate structures with a hard mask pattern, an insulating layer, and a trench that exposes the gate conductive pattern, followed by a silicide layer formation using a metal layer that reacts with silicon, with an oxidation prevention layer, to prevent metal from entering voids and forming a silicide layer that reduces resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between word lines is reduced to increase integration density, then the integration density is improved, but voids are formed between word lines due to incomplete filling of insulating layers
Solution Approach 1:
The patent applies preliminary action by forming the insulating layer completely filling the space between word lines before subsequent processing steps. The insulating layer is deposited to a thickness that ensures complete filling of narrow spaces, preventing void formation before metal deposition occurs. This preliminary complete filling approach prevents the void formation problem that would otherwise occur when design rules are reduced.
2Ease of manufacture
If metal layer is deposited on the semiconductor substrate prior to forming silicide layer, then the silicide formation is enabled, but metal flows into voids and causes stringer problems
Solution Approach 1:
The patent applies preliminary anti-action by completely filling potential void spaces with the insulating layer before the metal deposition step. By ensuring the insulating layer completely fills the space between word lines and covers the substrate surface, the method prevents metal from flowing into voids during subsequent metal layer formation. This preliminary preventive measure eliminates the stringer problem source before it can occur.
3Manufacturing precision
If the insulating layer thickness is increased to prevent void formation, then the void filling is improved, but the top surface of the insulating layer becomes non-coplanar with gate structures
Solution Approach 1:
The patent applies segmentation by dividing the insulating layer formation into distinct functional portions: a first portion that completely fills the space between word lines and prevents void formation, and a second portion that provides surface planarity. This segmentation allows each portion to optimize its specific function - the first portion ensures complete filling for void prevention, while the second portion is planarized to be coplanar with gate structure top surfaces.
Solution Approach 2:
The patent applies partial action by forming the insulating layer with different thicknesses in different regions. The insulating layer is formed to a greater thickness in regions between word lines to ensure complete filling and void prevention, while being planarized in regions with gate structures to achieve coplanarity. This partial thickness variation allows simultaneous achievement of complete filling and surface planarity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively prevents the formation of voids between gate structures, thereby avoiding stringer issues and reducing interconnection resistance by ensuring complete coverage and reaction of the metal layer with the silicon, enhancing the semiconductor device's performance.
Implementation Method 1
forming a silicide layer on the gate conductive pattern by performing an annealing process after forming a metal layer on the structure including the trench
Implementation Method 2
forming an oxidation prevention layer on the substrate including the metal layer prior to the annealing process
Data Source
AI summary
A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern.