Monolithic III-V and Silicon Integration With Shared Electrical Isolation
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Solution Overview
Problem
The integration of high-electron-mobility transistors with silicon-based devices on the same chip is challenging due to complexity in processes, such as wafer bonding and hybrid substrates with different crystalline orientations.
Innovation Solution
A substrate structure with a device layer, a handle substrate, and a buried insulator layer, where a III-V compound semiconductor layer and a silicon layer are formed on the device layer, enabling the creation of p-n junctions and device structures like Schottky diodes and transistors without requiring complex manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If wafer bonding or hybrid substrates with different crystalline orientations are used to integrate III-V compound semiconductor devices with silicon-based devices, then device integration is achieved, but manufacturing complexity increases significantly
Solution Approach 1:
The patent merges III-V compound semiconductor layers and silicon layers into a single integrated structure on a common substrate. The method combines epitaxial growth of different semiconductor materials with selective removal and bonding processes to create a unified device structure, eliminating the need for separate wafer bonding or hybrid substrate approaches and thereby reducing manufacturing complexity while achieving diverse device integration.
2Reliability
If III-V compound semiconductor and silicon layers are integrated on the same substrate, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The patent segments the substrate into distinct device regions with different crystalline orientations (first device region with first crystalline orientation and second device region with second crystalline orientation). This segmentation allows independent optimization of each region for specific device types while maintaining overall integration. The selective removal and bonding of segments enables complex device integration without requiring complex fabrication processes for the entire substrate.
3Adaptability or versatility
If diverse device types are integrated on a single chip, then functionality is enhanced, but manufacturing cost increases due to process complexity
Solution Approach 1:
The patent creates a universal substrate structure that can accommodate multiple device types through selective epitaxial growth and processing. The common substrate and buried insulator layer serve multiple functions: providing mechanical support, enabling electrical isolation, and facilitating diverse device integration. This multi-functional approach enhances device functionality while avoiding the need for separate manufacturing lines for different device types, thereby reducing overall manufacturing cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for monolithic co-integration of III-V and silicon-based devices on a single substrate, reducing complexity and improving operational parameters with lower power loss and increased reliability.
Implementation Method 1
a buried insulator layer between the handle substrate and the device layer
Implementation Method 2
The doped region and the device layer define a p-n junction
Implementation Method 3
a first device structure includes a gate structure on the first semiconductor layer
Data Source
AI summary
Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.