MTJ Stack Layout for Multi-Type MRAM on One IC
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Solution Overview
Problem
Existing MRAM integration schemes face challenges in fabricating different types of MRAM devices on a single IC without substantial performance tradeoffs, particularly due to the need for varying free layer thicknesses and critical dimensions to meet thermal stability and response time requirements, which incurs additional costs and complexity.
Innovation Solution
Implementing a single-IC MRAM integration scheme where all MRAM devices have a uniform free layer thickness, with different magnetic tunnel junction (MTJ) critical dimensions to vary current density and response time, allowing for simultaneous fabrication of reflow-MRAM, NvMRAM, and OTP MRAM on one IC, or RAM-like, OTP MRAM, and NvMRAM on another, using specific MTJ stack configurations and processing techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different free layer thicknesses are used to meet thermal stability and response time requirements, then device performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies local quality by varying the MTJ critical dimensions (area) in different regions of the same layer rather than changing the free layer thickness. This allows different MRAM devices on the same IC to have different current densities and response times while maintaining uniform free layer thickness, thus resolving the contradiction between performance optimization and manufacturing simplicity
Solution Approach 2:
The patent changes the critical parameter from free layer thickness to MTJ critical dimension (area). By adjusting the MTJ area while keeping the free layer thickness uniform, the invention achieves different thermal stability and response time characteristics without requiring complex multi-thickness fabrication processes, thereby resolving the technical contradiction
2Reliability
If different free layer thicknesses are used to meet thermal stability and response time requirements, then device performance is improved, but manufacturing cost increases
Solution Approach 1:
The patent implements local quality by creating region-specific MTJ critical dimensions within a uniform free layer thickness structure. This approach allows different performance characteristics (thermal stability and response time) to be achieved through area variation rather than thickness variation, eliminating the need for expensive additional fabrication steps and reducing manufacturing costs
Solution Approach 2:
The patent achieves multi-functionality by using a single uniform free layer thickness that serves multiple MRAM device types simultaneously. By varying only the MTJ critical dimensions, the same layer structure can fulfill different performance requirements, reducing manufacturing complexity and cost while maintaining diverse device functionalities
3Reliability
If varying MTJ critical dimensions are used to adjust current density and response time, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent shifts the optimization parameter from free layer thickness to MTJ critical dimension (area). This parameter change allows for more flexible and precise control of current density and response time, as area can be varied more easily during patterning processes without the stringent precision requirements associated with controlling thin film thicknesses
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the simultaneous fabrication of various MRAM devices on a single IC with reasonable cost and performance, meeting diverse thermal stability and response time requirements without significant performance tradeoffs, by leveraging uniform free layer thickness and tailored MTJ critical dimensions.
Implementation Method 1
depositing a magnetic tunnel junction (MTJ) stack over the bottom electrode layer
Data Source
AI summary
A semiconductor device according to the present disclosure includes a first conductive feature and a second conductive feature in a first dielectric layer, a buffer layer over the first dielectric layer, a second dielectric layer over the buffer layer, a first bottom via extending through the buffer layer and the second dielectric layer, a second bottom via extending through the buffer layer and the second dielectric layer, a first bottom electrode disposed on the first bottom via, a second bottom electrode disposed on the second bottom via, a first magnetic tunnel junction (MTJ) stack over the first bottom electrode, and a second MTJ stack over the second bottom electrode. The first MTJ stack and the second MTJ stack have a same thickness. The first MTJ stack has a first width and the second MTJ stack has a second width greater than the first width.


