Semiconductor Fabrication Planarization via Sacrificial Layer Oxidation

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Solution Overview

Problem

Existing semiconductor device fabrication processes face challenges in achieving planarity of layers, which affects the characteristics of variable resistance elements like Magnetic Tunnel Junctions, leading to potential curvature and deterioration of performance.

Innovation Solution

A method involving the formation of inter-layer dielectric and sacrificial layers, selective etching, and natural oxidation to create a planar surface for the variable resistance element, ensuring the bottom electrode and inter-layer dielectric have co-planar surfaces, preventing conductive byproducts and maintaining desired characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If conventional fabrication processes are used to form the bottom electrode and inter-layer dielectric, then the layers can be formed, but planarity is not achieved leading to curvature and performance deterioration

Engineering Contradiction:

Improveplanarity of bottom electrode and inter-layer dielectric surfacesVSAvoidfabrication process complexity

Core Design Contradiction:

Manufacturing precisionVSEase of manufacture

Solution Approach 1:

A planarization layer is formed over the inter-layer dielectric layer before forming the variable resistance element. This preliminary action ensures that the surface is planarized in advance, preventing curvature of the bottom electrode and inter-layer dielectric, and ensuring desired characteristics of the variable resistance element without requiring complex post-processing steps.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The fabrication process is segmented into distinct steps: forming the bottom electrode, forming the inter-layer dielectric, forming the planarization layer, and then forming the variable resistance element. This segmentation allows each layer to be optimized independently for planarity and performance, resolving the contradiction between manufacturing precision and ease of manufacture.

Inventive Principle:

Principle #1Segmentation

2Reliability

If the bottom electrode extends beyond the inter-layer dielectric, then connection is ensured, but conductive byproducts are generated affecting device performance

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidconductive byproducts

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The planarization layer acts as an intermediary between the bottom electrode and the variable resistance element. It covers any conductive byproducts that may be present, preventing them from affecting device performance while maintaining reliable electrical connection. The planarization layer mediates between the need for robust connection and the need to eliminate harmful conductive byproducts.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful conductive byproducts are effectively removed or isolated by the planarization layer, which provides a clean, non-conductive surface for the variable resistance element. This extraction of harmful factors ensures reliability without compromising connection integrity.

Inventive Principle:

Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach simplifies the fabrication process and enhances the planarity of the variable resistance element, improving its characteristics by preventing curvature and ensuring effective data storage without electrical leakage.

Implementation Method 1

selective etching, and natural oxidation to create a planar surface for the variable resistance element

Methodology Applied

Scientific EffectSelective etching:

Implementation Method 2

oxidizing the protruded first portion of the conductive pattern without oxidizing the second portion of the conductive pattern

Methodology Applied

Scientific EffectOxidation: Oxidation

Implementation Method 3

removing the oxidized first portion of the conductive pattern to expose a top of the second portion of the conductive pattern

Methodology Applied

Scientific EffectEtching:

Data Source

PatentUS9818936B2Method for fabricating semiconductor device

Publication Date: 2017.11.14 SK HYNIX INC

AI summary

A method for fabricating a semiconductor device includes: forming an inter-layer dielectric layer and a sacrificial layer over a substrate so that the sacrificial layer covers the inter-layer dielectric layer; forming a conductive pattern that is coupled with a portion of the substrate while penetrating through the inter-layer dielectric layer and the sacrificial layer; protruding a first portion of the conductive pattern by removing the sacrificial layer while maintaining a second portion of the conductive pattern inside the inter-layer dielectric layer; oxidizing the protruded first portion of the conductive pattern without oxidizing the second portion of the conductive pattern; removing the oxidized first portion of the conductive pattern to expose a top of the second portion of the conductive pattern; and forming a variable resistance element on top of the conductive pattern to couple a bottom of the variable resistance element with the top of the second portion of the conductive pattern.