Reconstructed 3DIC Layout With Active Die-to-Die Stitching
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Solution Overview
Problem
Conventional 3D integrated circuit (3DIC) packaging approaches are limited by passive silicon interposers and coarse interconnect density, requiring larger bottom dies and resulting in low yields, whereas the proposed solution allows for heterogeneous active dies with embedded communication bridges, enabling reduced die sizes and flexible functionality.
Innovation Solution
The solution involves reconstructing 3DIC structures where each die functions as both a functional chip and a stitching device, with a communication path between dies, using hybrid bonding and microbumps to connect multiple package levels, allowing for reduced die sizes and flexible functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional 3DIC packaging approaches use passive silicon interposers with coarse interconnect density, then the structure is simple to manufacture, but the die size must be large and yields are low
Solution Approach 1:
The patent segments the interconnect function by replacing the monolithic passive silicon interposer with multiple active dies that each provide localized interconnection. This segmentation enables fine-grained interconnect density while distributing complexity across multiple functional units rather than requiring a single complex interposer structure.
Solution Approach 2:
The patent makes dies multi-functional by requiring them to serve both as functional computing units and as interconnection/stitching devices. This eliminates the need for separate passive interposers, achieving high interconnect density while reducing overall structural complexity through functional consolidation.
2Productivity
If conventional approaches require large bottom dies to accommodate passive interposers, then manufacturing is simpler, but yields are reduced
Solution Approach 1:
The patent transitions from a 2D layout constrained by the bottom die footprint to a 3D stacked architecture where vertical interconnections through TSVs enable high-density routing without increasing the lateral die area. This dimensional change allows smaller dies while maintaining or improving yield.
Solution Approach 2:
The patent implements nesting by placing multiple functional dies and interconnection structures in vertical layers, with each layer containing smaller functional units that are stacked to achieve the required total functionality. This enables reduced individual die sizes while maintaining system-level performance and improving yield through better utilization of each die's area.
3Quantity of substance
If each die functions only as a functional chip, then the design is simpler, but the interconnect fabric density is reduced
Solution Approach 1:
The patent applies multi-functionality by designing each die to simultaneously perform computational functions and provide interconnection services to adjacent dies. This dual role increases the quantity of interconnect pathways available in the fabric while maintaining functional flexibility, as each die can be configured for different functional roles depending on system requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a high-density interconnect fabric among all dies, reducing the need for large bottom dies and improving yields by incorporating active devices within each die for communication bridges, facilitating smaller die sizes and minimalist functionality.
Implementation Method 1
Bonding of the second plurality of dies to the first reconstructed wafer can utilize hybrid bonding in an embodiment
Data Source
AI summary
Reconstructed 3DIC structures and methods of manufacture are described. In an embodiment, one or more dies in each package level of a 3DIC are both functional chips and/or stitching devices for two or more dies in an adjacent package level. Thus, each die can function as a communication bridge between two other dies/chiplets in addition to performing a separate chip core function.