TFT Array Substrate with Integrated Source Drain and Capacitor Electrodes

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Solution Overview

Problem

The complexity and cost of photolithography processes in manufacturing OLED displays are increased due to the need for multiple masks, leading to higher manufacturing time and costs, and the patterning process is intricate.

Innovation Solution

A method for manufacturing a thin film transistor (TFT) array substrate and OLED display that simplifies the process by using fewer masks, with a TFT structure featuring a substrate with a TFT, capacitor, and pixel electrode, where the active layer overlaps source and drain electrodes and a gate electrode, and a second insulating layer covers the gate and upper capacitor electrode, allowing for integral formation and reduced etching resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple masks are used in photolithography process to form TFT patterns, then patterning precision is improved, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvepatterning precisionVSAvoidprocess complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent combines the formation of source electrode, drain electrode, and capacitor electrode into a single photolithography step using one mask pattern. This merging of multiple patterning operations into one step reduces the total number of masks required while maintaining the necessary patterning precision for TFT fabrication.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single mask pattern serves multiple functions by simultaneously defining the source electrode, drain electrode, and capacitor electrode regions. This multi-functional mask design eliminates the need for separate masks for each electrode, simplifying the overall photolithography process while achieving precise patterning.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Manufacturing precision

If multiple photolithography steps are performed to form electrodes and capacitor, then manufacturing precision is improved, but loss of time increases

Engineering Contradiction:
Improvepatterning precisionVSAvoidmanufacturing time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

Multiple electrode formations (source, drain, capacitor) that previously required separate photolithography steps are merged into a single patterning operation. This consolidation maintains the precision needed for each electrode while significantly reducing the total manufacturing time by eliminating sequential processing steps.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If source and drain electrodes are formed separately from active layer, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improveelectrode positioning precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The source electrode, drain electrode, and capacitor electrode are formed as an integrated structure in a single photolithography step. This merging approach maintains precise electrode positioning through the unified mask pattern while simplifying the overall device structure by eliminating the need for separate formation processes and alignment steps.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10593711B2Method of manufacturing OLED display including thin film transistor having both source and drain formed over and patterned together with semiconductor layer
Publication Date: 2020.03.17 SAMSUNG DISPLAY CO LTD
  • US10593711B2 patent drawing
  • US10593711B2 patent drawing
  • US10593711B2 patent drawing

AI summary

A TFT array substrate, OLED display including the same, and a manufacturing method of the OLED display are disclosed. In one aspect, the TFT array substrate includes a substrate and a TFT formed over the substrate. The TFT includes an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer interposed between the gate electrode and the source and drain electrodes. Each of the source and drain electrodes is interposed between the active layer and the first insulating layer. The TFT array substrate also includes a capacitor formed over the substrate and having lower and upper electrodes and a pixel electrode electrically connected to the TFT.