Shared Data-Line Memory Chips With ODT and Equalizer Training
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Solution Overview
Problem
High-speed communication between controllers and memory devices in systems with multiple memory chips faces challenges in signal integrity and noise reduction due to varying signal path characteristics and inter-symbol interference, leading to inefficiencies in training operations and data transmission.
Innovation Solution
The memory device selects specific receivers for each data signal line and sets on-die termination (ODT) resistors to optimal resistance values based on mode register settings, and performs training operations to determine the amplification strength of equalizer circuits, allowing simultaneous training of multiple memory chips and improving signal reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple memory chips share a plurality of data signal lines, then communication speed and data transmission capacity are improved, but signal integrity deteriorates due to varying signal path characteristics and inter-symbol interference
Solution Approach 1:
The patent applies local quality by configuring different ODT resistance values for different receivers based on their specific signal path characteristics. Each receiver's ODT resistor is individually optimized according to its local signal quality, allowing simultaneous high-speed communication across multiple chips while maintaining signal integrity through localized impedance matching.
Solution Approach 2:
The patent changes the ODT resistance parameter dynamically through training operations. During training, different resistance values are tested and the optimal value is selected for each receiver based on measured signal quality metrics. This parameter optimization enables high-speed communication while compensating for signal degradation in shared data lines.
2Reliability
If training operations are performed for each memory chip individually, then signal amplification optimization is achieved, but training time increases
Solution Approach 1:
The patent merges training operations for multiple memory chips into a single simultaneous training process. By coordinating the training of multiple chips together and using parallel evaluation of ODT resistance values, the system achieves signal amplification optimization for all chips while reducing total training time compared to sequential individual training.
Solution Approach 2:
The patent performs preliminary grouping of memory chips into first and second groups before conducting training operations. This preliminary organization allows for systematic and efficient training sequences, where training results from one group can inform the training of subsequent groups, reducing redundant operations and overall training time.
3Reliability
If ODT resistors are set to different resistance values for different receivers, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal ODT control mechanism that manages multiple ODT resistors through a unified training and selection process. The same training operations and selection logic are applied across all receivers, providing a multi-functional solution that handles different resistance value configurations without requiring separate control circuits for each receiver, thus managing complexity efficiently.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces training time and enhances the efficiency of data transmission by optimizing signal amplification and noise reduction across multiple memory chips sharing a channel, ensuring consistent signal integrity and reliability.
Implementation Method 1
setting an amplification strength of an equalizer circuit of each first receiver by performing training operations
Implementation Method 2
setting each ODT resistor which is connected to a first receiver to a first resistance value
Data Source
AI summary
An operating method of a memory device includes selecting a receiver from a plurality of receivers of each memory chip of a plurality of memory chips included in the memory device as a first receiver. The plurality of memory chips share a plurality of data signal lines, each memory chip includes a plurality of on-die termination (ODT) resistors, and the plurality of ODT resistors are respectively connected to the plurality of receivers of each memory chip. The method further includes setting each ODT resistor which is connected to a first receiver to a first resistance value, setting ODT resistors which are connected to receivers which are not first receivers to a second resistance value, and setting an amplification strength of an equalizer circuit of each first receiver by performing training operations. Each data signal line of the plurality of data signal lines is respectively connected to a first receiver.