PMOS Transistor Silicon Germanium Strain Contact Resistance
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Solution Overview
Problem
As semiconductor devices integrate more densely, reducing the size of transistors and contact plugs increases contact resistance, degrading current characteristics and obstructing high-speed operation.
Innovation Solution
A semiconductor device with a PMOS transistor in a peripheral circuit region is formed over a silicon germanium layer with a compressive strain structure, using selective epitaxial growth to create a silicon germanium layer with a specific germanium mole ratio, enhancing hole mobility in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of the contact plug is reduced to accommodate high integration, then the area occupied by the device is reduced, but the contact resistance between the silicon substrate and the contact plug is increased
Solution Approach 1:
The patent changes the material composition parameter by introducing a silicon germanium layer with controlled germanium concentration (5-35 atomic %) beneath the contact plug. This material parameter change reduces contact resistance without increasing the contact plug area, thereby resolving the contradiction between device miniaturization and contact reliability.
Solution Approach 2:
The patent employs a composite structure consisting of a silicon germanium layer combined with the silicon substrate. The silicon germanium layer serves as an intermediate material that facilitates better electrical contact, effectively reducing contact resistance while maintaining the reduced contact plug dimensions required for high integration.
2Area of moving object
If the transistor size is reduced for high integration, then the device area is reduced, but the current characteristic is degraded
Solution Approach 1:
The patent modifies the material composition by introducing a silicon germanium layer with specific germanium concentration (5-35 atomic %) to alter the electrical properties of the channel region. This parameter change enhances hole mobility and improves current characteristics while maintaining the reduced transistor size required for high integration.
Solution Approach 2:
The patent applies local quality modification by forming a silicon germanium layer specifically in the channel region of the transistor. This localized material modification enhances the electrical properties where needed (in the channel) without affecting other parts of the device, thereby improving current characteristics while maintaining overall device miniaturization.
3Length of moving object
If the channel length is shortened for high integration, then the transistor size is reduced, but the hole mobility is decreased
Solution Approach 1:
The patent changes the material composition parameter by introducing a silicon germanium layer with controlled germanium concentration (5-35 atomic %) in the channel region. This material parameter change compensates for the shortened channel length by enhancing hole mobility through material properties, thereby maintaining device performance despite reduced channel dimensions.
Solution Approach 2:
The patent employs a composite material structure where a silicon germanium layer is integrated into the silicon channel. This composite structure provides enhanced hole mobility through the silicon germanium material properties, compensating for the reduced channel length and maintaining effective device operation in the high integration context.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance and improves current characteristics, enabling high-speed operation by increasing hole mobility in the channel region.
Implementation Method 1
forming a PMOS transistor of an upper layer over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region
Implementation Method 2
The silicon germanium layer is formed by a selective epitaxial growth
Data Source
AI summary
A semiconductor device includes a PMOS transistor of a peripheral circuit region. The PMOS transistor is formed over a silicon germanium layer to have a compressive strain structure, thereby increasing hole mobility of a channel region in operation of the device. The semiconductor device may include a second active region including a silicon layer connected to a first active region of a semiconductor substrate, a silicon germanium layer formed over the silicon layer expected to be a PMOS region, and a PMOS gate formed over the silicon germanium layer.