Memory Device Word Line Voltage Refresh Peak Current Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Memory devices face challenges in maintaining word line voltages during idle periods, leading to potential read errors due to voltage discharge, which can result in peak current exceeding specifications, potentially quenching the power supply and affecting battery lifetime.

Innovation Solution

Implementing a power-saving technique for the first word line voltage refresh or read operation after powering up, including reducing the ramp up rate and allocating additional time, attaining refresh or read pass voltage in multiple steps with reduced peak magnitude, and initiating ramp up for different groups or blocks at different times, based on programmed blocks or temperature.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If word line voltage refresh operation is performed at normal speed, then read operation reliability is improved, but peak current consumption increases and may quench the power supply

Engineering Contradiction:
Improveread operation reliabilityVSAvoidpeak current consumption
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent applies dynamics by adjusting the ramp-up rate of word line voltage based on operational context. During the first refresh operation after power-up, a reduced ramp-up rate is used to limit peak current. Subsequent refresh operations use normal ramp-up rates, dynamically adapting the voltage transition characteristics to different system states to balance reliability and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage ramp-up rate parameter from its normal value to a reduced value during the first refresh operation after power-up. This parameter modification directly controls the peak current magnitude, ensuring it remains below the quenching threshold while still achieving the necessary voltage refresh to maintain read operation reliability.

Inventive Principle:
Principle #35Parameter changes

2Power

If reduced ramp up rate is used for word line voltage refresh, then peak current consumption is reduced, but operation time increases

Engineering Contradiction:
Improvepeak current consumptionVSAvoidrefresh operation time
Core Design Contradiction:
PowerVSLoss of time

Solution Approach 1:

The patent implements periodic action by performing the time-consuming reduced-speed refresh operation only once after power-up, while subsequent refresh operations use the faster normal ramp-up rate. This periodic application of the time-intensive process minimizes cumulative time loss while ensuring the critical first refresh maintains adequate current levels for reliability.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent performs the preliminary word line voltage refresh operation with reduced ramp-up rate immediately after power-up to establish stable voltage levels before normal operations begin. This preliminary action ensures the memory device is properly initialized and ready for subsequent high-speed operations, preventing future reliability issues that would require additional time-consuming corrections.

Inventive Principle:
Principle #10Preliminary action

3Loss of energy

If word line voltage is not refreshed during idle periods, then power consumption is reduced, but voltage discharge occurs leading to read errors

Engineering Contradiction:
Improvepower consumptionVSAvoidread operation reliability
Core Design Contradiction:
Loss of energyVSReliability

Solution Approach 1:

The patent implements periodic word line voltage refresh operations during idle periods to maintain voltage levels and prevent discharge. By refreshing voltages at appropriate intervals rather than continuously, the system maintains read operation reliability while minimizing power consumption during standby states.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20220366990A1Read operation or word line voltage refresh operation in memory device with reduced peak current
Publication Date: 2022.11.17 SANDISK TECHNOLOGIES LLC
  • US20220366990A1 patent drawing
  • US20220366990A1 patent drawing
  • US20220366990A1 patent drawing

AI summary

Apparatuses and techniques are described for reducing peak current consumption in a memory device when performing a word line voltage refresh operation or a read operation. When a word line voltage refresh operation or read operation is performed for the first time after a memory device powers up, the operation is performed with a power-saving technique such as reducing a ramp up rate of a voltage pulse, ramping up the voltage pulse in multiple steps, initiating the ramp up for different groups of word lines in a block at different times, initiating the ramp up for different blocks of word lines at different times, and reducing the number of blocks which are refreshed concurrently. When an additional word line voltage refresh operation or read operation is subsequently performed, the power-saving technique can be omitted.