Display Device Fanout Area Reduction via Overlapping Conductive Loops

The patent transitions from a planar arrangement of conductive lines to a three-dimensional overlapping configuration. Multiple conductive lines are arranged in different layers that overlap vertically, allowing signals to be transmitted through stacked conductive structures rather than requiring lateral spacing. This dimensional transition enables more conductive lines to be packed into a smaller planar footprint, reducing the fanout area while maintaining high resolution connectivity.

The patent implements a nested arrangement where conductive lines are organized in hierarchical layers with overlapping structures. Inner conductive lines are positioned within the projection area of outer conductive lines by utilizing vertical stacking. This nesting approach allows multiple conductive pathways to share the same planar space through layered construction, effectively reducing the overall area required for the fanout region while supporting increased resolution requirements.

By moving conductive line routing into the vertical dimension through overlapping layers, the patent reduces planar complexity. The multi-layer stacked configuration allows conductive lines to cross and connect without requiring complex lateral routing, simplifying the overall integration process despite the reduced area. The vertical stacking provides an intuitive organizational structure that manages complexity through spatial hierarchy.

The patent merges multiple conductive line functions into overlapping vertical structures where multiple signals share the same planar footprint through layered construction. This consolidation approach combines what would traditionally require separate lateral pathways into compact stacked arrangements, reducing the fanout area while the modular layered design maintains manufacturing feasibility through standardized stacking processes.