Array Substrate Data Line Vertical Separation Reduces Crosstalk

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Solution Overview

Problem

Existing display technologies face issues with parasitic capacitance and signal crosstalk between data lines and common electrodes, leading to increased power consumption and reduced picture quality, and are inefficient in manufacturing processes due to the need for multiple mask plates and steps.

Innovation Solution

The array substrate design features a data line and common electrode positioned on opposite sides of the base substrate, with a thin film transistor and conductive layers formed using a single patterning process, minimizing parasitic capacitance and signal crosstalk, and eliminating the need for additional mask plates and resin layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If data line and common electrode are positioned on the same side of the base substrate, then manufacturing process is simpler, but parasitic capacitance and signal crosstalk increase leading to higher power consumption and reduced picture quality

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidpower consumption
Core Design Contradiction:
Ease of manufactureVSLoss of energy

Solution Approach 1:

The patent positions the data line on the first surface of the base substrate and the common electrode on the second surface, utilizing the third dimension (vertical separation through the substrate thickness) to reduce parasitic capacitance and signal crosstalk, thereby lowering power consumption while maintaining manufacturing feasibility

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Manufacturing precision

If multiple mask plates and resin layers are used in manufacturing, then manufacturing precision can be improved, but device complexity and manufacturing time increase

Engineering Contradiction:
Improvepattern alignment precisionVSAvoidnumber of mask plates and layers
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges the formation of the data line and common electrode into a single patterning process by positioning them on opposite surfaces of the base substrate, eliminating the need for separate mask plates and resin layers, thereby reducing device complexity and manufacturing steps while maintaining pattern alignment precision

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If multiple mask plates and resin layers are used in manufacturing, then manufacturing precision can be improved, but productivity decreases due to increased manufacturing steps

Engineering Contradiction:
Improvepattern alignment precisionVSAvoidmanufacturing throughput
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent combines the patterning of data lines and common electrodes into a single manufacturing step by utilizing the base substrate as a natural separator, eliminating multiple sequential steps involving additional mask plates and resin layers, thereby increasing manufacturing throughput while preserving pattern alignment precision

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11437409B2Array substrate and manufacturing method thereof, and display device
Publication Date: 2022.09.06 BOE TECHNOLOGY GROUP CO LTD
  • US11437409B2 patent drawing
  • US11437409B2 patent drawing
  • US11437409B2 patent drawing

AI summary

An array substrate and a manufacturing method thereof, and a display device. The array substrate includes: a base substrate, including a first surface and a second surface opposite to each other, and a through-hole penetrating the base substrate from the first surface to the second surface; a data line on the first surface of the base substrate, the data line being at least partially filled in the through-hole; a thin film transistor on the second surface of the base substrate, the thin film transistor including a source electrode and a drain electrode, and the source electrode being electrically connected to the data line.