Double-source semiconductor device with segmented source layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional three-dimensional non-volatile memory devices face challenges in manufacturing and performance due to increased complexity and reduced cell current as the stacked structure height increases, leading to deteriorated operating characteristics during program or erase operations.
Innovation Solution
The semiconductor device incorporates a source layer with grooves, a stacked structure, and channel layers passing through the insulating layer, with voids and silicide layers to enhance manufacturing ease and improve performance by reducing contact resistance and increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the stacked structure height is increased to improve integration density, then the degree of integration is improved, but the manufacturing difficulty increases due to etch process complexity
Solution Approach 1:
The source layer is divided into multiple regions (first source layer, second source layer with first and second regions) at different heights. This segmentation allows the etch process to access and form contact holes to different source layer regions independently, simplifying the manufacturing process while maintaining high integration density through the stacked structure.
Solution Approach 2:
The patent transitions from a conventional two-dimensional planar structure to a three-dimensional stacked structure with source layers at different heights. This dimensional change enables higher integration density by stacking memory cells vertically while using selective etching processes to access different layers, thereby simplifying the overall manufacturing complexity despite the increased height.
2Productivity
If the string is arranged in a U shape to improve integration density, then the degree of integration is improved, but the cell current is reduced due to increased channel length
Solution Approach 1:
The source layer is segmented into first and second regions at different heights, allowing the channel to be formed more directly between the channel layer and the appropriate source layer region. This segmentation enables a more efficient current path that reduces the effective channel length compared to a U-shaped arrangement, thereby maintaining higher cell current while achieving improved integration density through vertical stacking.
3Productivity
If the stacked structure height is increased to improve integration density, then the degree of integration is improved, but the operating characteristics deteriorate due to insufficient current flow
Solution Approach 1:
The source layer is divided into first and second regions at different heights, enabling optimized current flow paths for program and erase operations. This segmentation allows sufficient current to reach the memory cells in the stacked structure by providing direct access through contact holes to the appropriate source layer regions, thereby maintaining good operating characteristics while achieving high integration density.
Solution Approach 2:
The second source layer acts as an intermediary between the channel layer and the first source layer. This intermediary structure facilitates efficient current flow during program and erase operations by providing a conductive path that bridges the vertical distance in the stacked structure, ensuring sufficient current reaches the memory cells while maintaining the high integration density benefits of the stacked architecture.
Data Source
AI summary
A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. The semiconductor device may include a second source layer including a first region interposed between the first source layer and the first insulating layer and second regions interposed between the first channel layers and the first insulating layer, wherein the second regions of the second source layer directly contact each other.