Bulk Wafer Switch Isolation Using Amorphous Inactive Regions
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Solution Overview
Problem
Non-SOI trap rich wafers provide poor switching capabilities and linearity due to dummy fill field effect transistor shapes, while high-resistivity SOI technologies offer better performance but at a high cost, necessitating a cost-effective solution that enhances switching linearity and harmonics without increasing expenses.
Innovation Solution
The implementation of bulk wafer switch isolation structures using a single crystalline bulk substrate with an active region, an inactive region separated by shallow trench isolation, and an amorphous layer formed by low energy argon implantation in the inactive region, which increases substrate resistivity and improves switching linearity and harmonics without the need for high energy implants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-resistivity SOI technologies are used, then switching linearity and harmonics are improved, but manufacturing cost increases considerably
Solution Approach 1:
The patent applies local quality by creating high resistivity only in the inactive regions of the substrate through selective argon ion implantation. The active regions maintain their original crystalline structure and electrical properties, while inactive regions are transformed to have high resistivity. This localized modification achieves the electrical isolation needed for improved switching linearity without requiring the entire substrate to be high-cost HR-SOI material.
Solution Approach 2:
The patent changes the physical and electrical parameters of the substrate material in inactive regions by using low-energy argon ion implantation. This process transforms the crystalline silicon in inactive regions into an amorphous, high-resistivity state. The parameter change occurs only where needed, converting standard bulk substrate into a structure that provides HR-SOI-like performance for isolation purposes while maintaining cost-effectiveness.
2Ease of manufacture
If standard bulk wafers are used, then manufacturing cost is reduced, but switching capabilities and coplanar waveguide linearity deteriorate due to dummy fill FET shapes
Solution Approach 1:
The patent converts the harmful effect of dummy fill structures in inactive regions into a beneficial high-resistivity isolation layer. By applying argon ion implantation to these previously problematic areas, the dummy fills are transformed into high-resistivity regions that provide electrical isolation. This turns what was previously a source of interference and poor linearity into an asset that improves switching capabilities.
Solution Approach 2:
The patent introduces argon ions as an intermediary to modify the electrical properties of inactive regions. The ion implantation process serves as a mediator that transforms the substrate material in inactive regions, creating a distinct high-resistivity layer that provides the necessary electrical isolation without requiring complete adoption of expensive HR-SOI substrate technology.
3Reliability
If high energy argon implant is used to create high resistive surface, then substrate resistivity increases, but device complexity and processing energy increase
Solution Approach 1:
The patent applies partial action by using low-energy argon ion implantation instead of high-energy implantation. The implantation energy is carefully controlled to be sufficient to create the desired amorphous, high-resistivity layer in the inactive regions, but not so high as to cause excessive damage or require complex recovery processes. This optimized energy level achieves the necessary resistivity increase with simpler processing.
Solution Approach 2:
The patent uses a disposable, single-step low-energy argon implantation process that creates the high-resistivity layer without requiring subsequent complex annealing or recovery steps. The process is designed to achieve the desired effect in one straightforward operation, avoiding the need for expensive, multi-step high-energy implantation and recovery sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances switching linearity and harmonics while reducing costs by creating a high resistive surface on bulk wafers without affecting active areas, thus offering a cost-effective alternative to high-resistivity SOI technologies.
Implementation Method 1
an amorphous layer formed by low energy argon implantation in the inactive region
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to bulk wafer switch isolation structures and methods of manufacture. The structure includes: a bulk substrate material; an active region on the bulk substrate material; an inactive region adjacent to the active region; and an amorphous material covering the bulk substrate material in the inactive region, which is adjacent to the active region.