Split-Gate Flash Memory Layout for Short-Free Source Contacts
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Solution Overview
Problem
The manufacturing process of split-gate type flash memory is complicated due to the need to remove a polysilicon layer for source line contact formation, and the spacer damage during etching can cause floating gate shorts, affecting performance.
Innovation Solution
A floating gate is disposed in a substrate and wrapped by a dielectric layer, allowing a source line contact to be formed between adjacent memory cells without additional etching processes, thereby preventing floating gate shorts and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon layer is formed over the source region as an erase gate, then the erase gate function is achieved, but additional etching steps are required to form source line contact openings, increasing process complexity
Solution Approach 1:
The patent segments the gate structure by forming the erase gate only in the channel region and using a separate polysilicon layer in the source region that does not require etching for contact formation. This segmentation allows the source line contacts to be formed directly through the polysilicon layer without additional etching steps, reducing process complexity while maintaining erase gate functionality.
Solution Approach 2:
The patent performs preliminary action by forming the polysilicon layer in the source region before contact formation, and designing it to be removable or penetrable without requiring subsequent etching steps. This preliminary structuring eliminates the need for additional etching processes to create source line contact openings.
2Ease of manufacture
If source line contacts are located at the edge of the memory cell array region, then contact formation is simplified, but the large distance difference between contacts and memory cells causes loading effect
Solution Approach 1:
The patent moves the source line contacts from the traditional edge location to positions between adjacent memory cells, utilizing the vertical dimension and the space between cells. This dimensional repositioning allows contacts to be closer to the memory cells they serve, reducing the distance difference and minimizing loading effect while still maintaining ease of manufacture through the polysilicon layer structure.
3Reliability
If a spacer is used to isolate the floating gate from other gates, then gate isolation is achieved, but the spacer is damaged in subsequent etching processes, causing floating gate contact with other gates
Solution Approach 1:
The patent extracts or removes the fragile spacer component from the gate isolation structure. Instead of using a spacer that requires precise protection during etching, the design directly forms the erase gate and polysilicon layer structures with inherent isolation, eliminating the spacer and its vulnerability to damage in subsequent etching processes.
Solution Approach 2:
The patent applies beforehand cushioning by designing a gate structure with built-in isolation features that protect against potential contact before etching processes occur. The erase gate and polysilicon layer are configured to maintain proper spacing and isolation through their structural design, providing prior protection against gate contact issues that would otherwise require spacer protection.
Data Source
AI summary
Provided are a flash memory and a manufacturing method thereof. The flash memory includes a floating gate disposed in a substrate, a first, a second and a third dielectric layers, a source region, a drain region, an erase gate on the second dielectric layer, and a select gate. The first dielectric layer is disposed between the floating gate and the substrate. The second dielectric layer covers the exposed surface of the floating gate. The source region is disposed in the substrate at one side of the floating gate and in contact with the first dielectric layer. The drain region is disposed in the substrate at another side of the floating gate and separated from the first dielectric layer. The select gate is disposed on the substrate between the floating gate and the drain region. The third dielectric layer is disposed between the select gate and the substrate.