Array Substrate Layout for LCD Splicing Alignment
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Solution Overview
Problem
The challenge in manufacturing large-size liquid crystal display panels is the need for multiple masks during splicing exposure, which can lead to splicing offsets and defects due to the lack of alignment marks within the display area, causing issues like dark or bright lines and abnormal displays.
Innovation Solution
The array substrate incorporates sub-pixel units with embedded alignment marks, including connection portions and via holes, to monitor and correct splicing offsets, ensuring accurate alignment and pattern positioning without occupying additional area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple masks are used for splicing exposure to manufacture large-size display panels, then the display size can be increased, but splicing offsets and alignment errors occur due to lack of alignment marks within the display area
Solution Approach 1:
The patent merges the alignment mark function with the pixel electrode structure by integrating connection portions into the pixel electrode pattern. The pixel electrode serves dual purposes: as a functional display element and as an alignment reference for splicing exposure, eliminating the need for separate alignment marks outside the display area.
Solution Approach 2:
The patent extends the alignment functionality from the traditional surrounding area (2D boundary) into the display area itself by using the pixel electrode pattern. The connection portions are distributed across multiple layers and positions within the display area, creating a three-dimensional alignment reference system that provides multiple detection points for offset correction.
2Area of stationary object
If alignment marks are placed in the surrounding area only, then the display area is maximized, but splicing offset detection is insufficient leading to defects like dark or bright lines
Solution Approach 1:
The patent implements a feedback mechanism for offset detection by incorporating connection portions that can be observed after splicing exposure. These connection portions serve as reference markers that provide feedback on alignment accuracy, allowing for detection and correction of splicing offsets before final product completion, thereby preventing display defects.
Solution Approach 2:
The patent performs preliminary alignment verification by designing connection portions that are formed during the splicing exposure process itself. The connection portions are created as part of the pixel electrode pattern before final product assembly, enabling early detection of alignment issues and preventing defect formation in the display area.
3Manufacturing precision
If connection portions are added to monitor splicing offsets, then alignment accuracy improves, but the structure complexity and manufacturing steps increase
Solution Approach 1:
The patent makes the pixel electrode structure universal by giving it multiple functions: it serves as both the functional pixel electrode for display and as the alignment mark for splicing exposure. The connection portions are not separate components but are integrated into the pixel electrode pattern itself, reducing overall structure complexity while maintaining alignment accuracy.
Solution Approach 2:
The pixel electrode structure serves itself by providing its own alignment reference function through the connection portions. Instead of requiring separate alignment marks or additional reference structures, the pixel electrode pattern inherently contains the necessary alignment information, allowing the structure to self-verify its positioning accuracy during splicing exposure.
Data Source
AI summary
An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.