Pixel-Array Substrate With Vertical Transfer Gate for Low Capacitance
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Solution Overview
Problem
Pixels with vertical transfer gates in camera image sensors exhibit high parasitic capacitance, which inhibits high conversion gain and limits the ability to produce quality images, especially in low-light conditions.
Innovation Solution
The implementation of a pixel-array substrate with a trench-based vertical-transfer-gate structure and a low-κ dielectric spacer to reduce parasitic capacitance, allowing for increased conversion gain and improved image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertical transfer gate structure is used to increase pixel density, then pixel density is improved, but parasitic capacitance increases
Solution Approach 1:
The patent transitions from a planar transfer gate structure to a vertical transfer gate structure by extending the gate into the depth dimension of the pixel. This dimensional change allows the transfer gate to control charge transfer between photodiodes and floating diffusion regions without occupying additional lateral space, thereby increasing pixel density while maintaining functional performance.
Solution Approach 2:
The patent embeds the transfer gate structure within the vertical depth of the pixel by forming it in a trench that extends into the substrate. This nesting approach allows the transfer gate to be positioned between the photodiode and floating diffusion region in the vertical dimension, enabling effective charge transfer control without increasing the lateral footprint of the pixel.
2Productivity
If vertical transfer gate structure is used to increase pixel density, then pixel density is improved, but conversion gain decreases
Solution Approach 1:
The patent introduces a low-κ dielectric material as an intermediary substance filling the trench surrounding the vertical transfer gate. This dielectric material acts as an electrical insulator with low permittivity, reducing the parasitic capacitance between the transfer gate and adjacent charge-carrying regions, thereby preserving conversion gain while enabling the vertical structure.
Solution Approach 2:
The patent changes the dielectric parameter of the material filling the trench from high-κ to low-κ. This parameter change reduces the parasitic capacitance formed between the vertical transfer gate and surrounding structures, directly improving conversion gain while maintaining the space-efficient vertical architecture.
3Ease of manufacture
If photodiode and floating diffusion region are laterally displaced, then transfer gate can be formed, but pixel density is limited
Solution Approach 1:
The patent resolves the lateral displacement requirement by forming the transfer gate in the vertical dimension through a trench extending into the substrate. This allows the photodiode and floating diffusion region to be vertically stacked rather than laterally displaced, enabling closer lateral spacing of pixels and thereby increasing pixel density.
Solution Approach 2:
The patent performs preliminary structuring of the substrate by forming the trench and positioning the vertical transfer gate before finalizing the photodiode and floating diffusion region formation. This preliminary action establishes the vertical charge transfer pathway in advance, allowing subsequent layers to be optimized for density without compromising transfer gate functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces parasitic capacitance, enhancing the conversion gain of image sensor pixels and enabling the capture of high-quality images, even in low-light conditions.
Implementation Method 1
Pixels with vertical transfer gates exhibit high parasitic capacitance between the vertical transfer gate and the floating diffusion region
Implementation Method 2
The recess is filled with a low-κ dielectric spacer
Implementation Method 3
Light reaching the photodiode generates photoelectrons
Data Source
AI summary
A pixel-array substrate includes (i) a semiconductor substrate including a photodiode region and a floating diffusion region, and (ii) a vertical-transfer-gate structure that includes a trench and a gate electrode. The trench is defined by a bottom surface and a sidewall surface of the substrate each located between a front substrate-surface and a back substrate-surface thereof. The trench extends into the substrate. In a cross-sectional plane perpendicular to the front substrate-surface and intersecting the floating diffusion region, the photodiode region, and the sidewall surface, (a) the trench is located between the floating diffusion region and the photodiode region, and (b) a top section of the sidewall surface is adjacent to the floating diffusion region. A gate electrode partially fills the trench such that the top section and a conductive-surface of the gate electrode in-part define a recess located between the floating diffusion region and the gate electrode.