Dual-Layer Gate Insulating Layer for Thin Film Transistor Stability
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Solution Overview
Problem
Current thin film transistors face challenges in achieving high mobility, stability, and reliability due to limitations in gate insulating layers, particularly in high-resolution display devices with short channel lengths and large s-factors, which affect their performance and manufacturing costs.
Innovation Solution
A thin film transistor design incorporating a gate insulating layer with two distinct layers having different dielectric constants, where the second gate insulating layer extends to the lateral and upper surfaces of the gate electrode, enhancing mobility and preventing defects, thereby improving stability and reliability without requiring additional mask processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single-layer gate insulating structure is used, then the device structure is simple, but mobility is insufficient and threshold voltage shifts occur
Solution Approach 1:
The gate insulating layer is divided into two distinct layers: a first gate insulating layer (e.g., SiO2 or Si3N4) and a second gate insulating layer (e.g., HfO2 or Al2O3). Each layer serves specific functions - the first layer provides basic insulation and interface quality, while the second layer with higher dielectric constant enhances gate control and prevents threshold voltage shifts, thereby improving reliability without excessive complexity
Solution Approach 2:
The patent employs composite gate insulating structure combining materials with different dielectric constants. The first gate insulating layer uses conventional materials like SiO2 (k≈3.9) or Si3N4 (k≈7.5), while the second layer uses high-k materials like HfO2 (k≈25) or Al2O3 (k≈10). This composite structure leverages the advantages of each material to achieve both stability and controlled complexity
2Manufacturing precision
If the channel length is shortened for high-resolution displays, then pixel density increases, but mobility decreases and s-factor increases
Solution Approach 1:
The patent changes the dielectric constant parameter of the gate insulating layer by introducing a second layer with higher k-value. This parameter change enhances the gate electric field control over the channel, compensating for the shortened channel length effects and maintaining mobility while enabling higher pixel density displays
3Reliability
If polycrystalline silicon is used for the active layer, then mobility and stability are improved, but manufacturing cost increases due to additional crystallization steps
Solution Approach 1:
The patent extracts the mobility enhancement function from the complex crystallization process and transfers it to the gate insulating layer design. By using a dual-layer gate insulating structure with high-k second layer, the system achieves poly-Si-like performance with a-Si or oxide semiconductor active layers, eliminating the need for additional crystallization steps while maintaining ease of manufacture
4Device complexity
If the gate insulating layer covers only the channel region, then the structure is simple, but defects occur at the gate electrode surfaces
Solution Approach 1:
The second gate insulating layer extends not only over the channel region but also onto the lateral and upper surfaces of the gate electrode, adding dimensional coverage. This extended coverage prevents defects at gate electrode surfaces and improves device stability without significantly increasing structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The dual-layer gate insulating approach increases mobility, prevents threshold voltage shifts, and enhances grayscale expression, stability, and reliability, facilitating the use of thin film transistors in high-resolution display devices while reducing manufacturing complexity.
Implementation Method 1
a gate insulating layer, at least a part of which is disposed between the active layer and the gate electrode, wherein the gate insulating layer includes a first gate insulating layer between the active layer and the gate electrode, and a second gate insulating layer having a dielectric constant different from that of the first gate insulating layer
Data Source
AI summary
A thin film transistor includes an active layer on a substrate, a gate electrode configured to be spaced from the active layer and partially overlapped with the active layer, and a gate insulating layer, at least a part of the gate insulating layer being disposed between the active layer and the gate electrode, wherein the gate insulating layer includes a first gate insulating layer between the active layer and the gate electrode, and a second gate insulating layer configured to have a dielectric constant (k) which is different from a dielectric constant of the first gate insulating layer, and disposed in a same layer as the first gate insulating layer, and wherein at least a part of the second gate insulating layer is disposed between the active layer and the gate electrode.