GaN Power Transistor Clamping Node for Avalanche and Isolation
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Solution Overview
Problem
Conventional GaN power transistors on silicon substrates face challenges with crosstalk and parasitic inductance, limiting high-frequency applications, and lack avalanche capability due to the absence of PN junctions, which is crucial for high-voltage applications like motor drives.
Innovation Solution
A semiconductor device with an engineered bulk silicon substrate featuring a high-side and low-side transistor separated by isolation structures, including a clamping diode at a heterojunction, providing intrinsic avalanche capability and reducing parasitic inductance through deep trench isolation and dielectric filling, and integrating Si PN junctions for enhanced voltage blocking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional GaN power transistors are fabricated on silicon substrates, then manufacturing cost is reduced and manufacturing precision is improved, but avalanche capability is lost due to absence of PN junctions
Solution Approach 1:
The silicon substrate is segmented into multiple regions with different doping types (N-type first silicon layer, P-type second silicon layer) to create distinct functional zones. This segmentation enables formation of PN junctions at specific interfaces while maintaining overall substrate integrity and manufacturing simplicity.
Solution Approach 2:
The patent creates a composite structure by integrating III-N heterostructure (GaN layer) with engineered bulk silicon substrate containing PN junctions. This composite approach combines the high-frequency advantages of GaN with the avalanche capability of silicon PN junctions, achieving both high-frequency operation and overvoltage protection.
2Reliability
If deep trench isolation structures are implemented, then electrical isolation is improved and crosstalk is eliminated, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The isolation approach segments the conductive paths between high-side and low-side transistors using deep trench structures filled with dielectric material. This physical segmentation creates electrical isolation that eliminates crosstalk while maintaining a relatively straightforward fabrication process using standard semiconductor manufacturing techniques.
3Speed
If parasitic inductance is reduced through isolation structures, then high-frequency performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent addresses parasitic inductance by extending isolation trenches deeply into the substrate vertically, utilizing the depth dimension to achieve effective electrical isolation. This vertical dimensionality change allows for adequate isolation without requiring extremely tight lateral tolerances, thereby reducing manufacturing precision requirements while still achieving high-frequency performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively eliminates crosstalk, enhances avalanche capability, and reduces parasitic inductance, enabling high-performance and cost-effective high-voltage switching applications by providing over-voltage protection and improved electrical isolation.
Implementation Method 1
GAN power transistor having a voltage clamping node with avalanche capability
Implementation Method 2
The wide-bandgap AlGaN/GaN heterostructure system of the nitride semiconductor barrier layer 110, induced by the spontaneous and piezoelectric polarization effects, yields two-dimensional electron gas (2DEG) channel 141
Data Source
AI summary
A semiconductor device with intrinsic avalanche capability is provided. The semiconductor device includes an engineered bulk silicon (EBUS) substrate having a first silicon layer and a second silicon layer formed above the first silicon layer, and a semiconductor heterostructure formed above the EBUS substrate. The semiconductor heterostructure comprises a high-side (HS) transistor and a low-side (LS) transistor. The HS transistor and the LS transistor are separated by a first isolation structure. The HS transistor has an input terminal (VIN) electrically connected to a clamping diode formed at a first heterojunction between the first and second silicon layers. The clamping diode and the HS transistor are separated by a second isolation structure.