3D Memory Device Layer-Selecting Transistors for Addressing
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Solution Overview
Problem
Designing and debugging three-dimensional memory devices is complicated due to the intricate electrical interconnections and addressing of memory cells across multiple layers, which requires innovative circuit designs to increase memory capacity effectively.
Innovation Solution
The use of thin-film-transistor (TFT) memory cells organized in planes, with layer-selecting transistors that allow for easy selection and decoding of memory cells across multiple layers, similar to two-dimensional memory arrays, using X and Y parameters for rows and columns and a Z parameter for layer selection, simplifying the addressing scheme and reducing redesign complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in multiple layers or planes to increase memory capacity, then memory capacity is improved, but device complexity increases due to intricate electrical interconnections and addressing requirements
Solution Approach 1:
The patent divides the three-dimensional memory device into multiple two-dimensional memory planes stacked vertically. Each plane is independently addressable and can be selectively activated. This segmentation allows the complex 3D memory to be broken down into simpler 2D units, making the electrical interconnections and addressing schemes more manageable while achieving high memory capacity through vertical stacking.
Solution Approach 2:
The patent transitions from traditional two-dimensional memory arrays to three-dimensional stacked memory planes by adding the vertical dimension (Z-axis). Multiple 2D memory planes are stacked along the vertical direction, allowing memory capacity expansion without increasing the footprint area. This dimensional change enables efficient space utilization while maintaining relatively simple interconnection schemes within each plane.
2Quantity of substance
If intricate circuit designs are used to connect electrical lines in every layer to the ground layer, then memory capacity is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent segments the memory device into independent 2D planes with localized interconnections. Each plane has its own simplified connection scheme to the ground layer, rather than requiring all layers to connect intricately to a single ground layer. This segmentation reduces manufacturing complexity while maintaining high memory capacity through vertical stacking of multiple planes.
3Quantity of substance
If memory cells are placed in multiple layers, then memory capacity is improved, but ease of operation deteriorates due to complicated addressing of memory cells across layers
Solution Approach 1:
The patent divides the 3D memory into separate 2D planes that can be independently selected and addressed. Each plane maintains its own simplified addressing scheme similar to traditional 2D memory, avoiding the need for complex 3D addressing. The segmentation allows operational simplicity within each plane while achieving high capacity through vertical stacking.
Solution Approach 2:
The patent adds a plane selection dimension to address memory cells in 3D stacked architecture. Instead of complex 3D coordinates, the system uses extended 2D addressing within selected planes, making operation easier. Multiple 2D planes are stacked vertically, allowing memory capacity expansion while maintaining relatively simple interconnection and addressing schemes within each plane.
Data Source
AI summary
The invention describes a semiconductor cell including a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region.