3D Memory Stack Layer Thickness Compensation
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Solution Overview
Problem
In 3D memory devices, the variation in channel hole width leads to undesirable topography, resulting in uneven programming/erase speeds and threshold voltage distribution, affecting memory cell performance and stability.
Innovation Solution
The thickness of conductor layers is nominally proportional to the channel structure width, while the thickness of dielectric layers is inversely proportional, compensating for the channel width variation and improving the erase state coupling effect and memory cell uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar scaling is used to increase memory density, then memory capacity increases, but manufacturing complexity and cost increase significantly as feature sizes approach lower limits
Solution Approach 1:
The patent transitions from planar (2D) memory cell scaling to three-dimensional (3D) stacking architecture, where memory cells are arranged vertically across multiple layers. This dimensional change allows continued density improvement without further reducing lateral feature sizes, thereby avoiding the manufacturing complexity and cost penalties associated with advanced planar scaling
2Ease of manufacture
If uniform layer thicknesses are used in the stack structure, then fabrication is simpler, but channel width variation causes uneven programming/erase speeds and threshold voltage distribution
Solution Approach 1:
The patent implements non-uniform layer thicknesses in the stack structure, where conductor layer thickness and dielectric layer thickness are locally adjusted based on the desired channel width at each vertical position. This local quality variation compensates for channel width differences, ensuring uniform programming/erase speeds and threshold voltage distribution across memory cells while maintaining fabrication feasibility through controlled deposition processes
Data Source
AI summary
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, the memory device includes a stack structure having interleaved a plurality of sacrificial layers and a plurality of dielectric layers over a substrate along a vertical direction. The memory device also includes a channel structure extending in the stack structure along the vertical direction. A thickness of at least one of the plurality of sacrificial layers is nominally proportional to a width of the channel structure at the same depth. A thickness of at least one of the plurality of dielectric layers is nominally inversely proportional to a width of the channel structure at the same depth.