3D Memory Device Layout Optimization via Vertical Stacking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the number of layers of word lines in 3D nonvolatile memory devices increases, the size of the memory cell array decreases, but the size of the peripheral circuit remains unchanged, leading to an overall increase in chip size, which is undesirable.
Innovation Solution
The memory device is designed with a first semiconductor layer containing a peripheral circuit and a second semiconductor layer stacked vertically with a memory cell array, where the length of the page buffer circuit in the first direction is different from the length of the memory cell array, allowing for efficient arrangement of circuit elements and reducing chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers of word lines is increased to increase memory capacity, then the size of the memory cell array is reduced, but the overall chip size increases because the peripheral circuit size remains unchanged
Solution Approach 1:
The patent applies dimensionality change by stacking semiconductor layers vertically (third direction) to arrange different circuit elements in three-dimensional space. The first semiconductor layer contains the peripheral circuit while the second semiconductor layer contains the memory cell array, allowing both to coexist without increasing the horizontal footprint. This vertical stacking resolves the contradiction by utilizing the vertical dimension to accommodate increased memory capacity while maintaining a compact chip size.
Solution Approach 2:
The patent segments the circuit into distinct functional blocks distributed across different semiconductor layers. The peripheral circuit is isolated in the first semiconductor layer, while the memory cell array is placed in the second semiconductor layer. This segmentation allows independent optimization of each region and enables the peripheral circuit to be positioned at optimal locations without constraining the memory array layout, thereby reducing overall chip size while maintaining capacity.
2Quantity of substance
If the size of the memory cell array is reduced by increasing word line layers, then more memory capacity is achieved, but the peripheral circuit elements cannot be efficiently arranged
Solution Approach 1:
The patent divides the circuit into separate semiconductor layers, placing peripheral circuit elements in the first layer and memory cell array elements in the second layer. This segmentation provides manufacturing ease by allowing independent layout and optimization of each region without interference from the other, while both regions benefit from the increased memory capacity achieved through vertical stacking.
Solution Approach 2:
By transitioning from two-dimensional planar arrangement to three-dimensional vertical stacking, the patent creates additional spatial freedom for arranging peripheral circuit elements. The first semiconductor layer can be positioned and dimensioned independently to optimize peripheral circuit layout, while the second layer accommodates the memory array, thus improving ease of manufacture without sacrificing capacity.
Data Source
AI summary
A memory device includes a first semiconductor layer including a peripheral circuit therein and a second semiconductor layer stacked on the first semiconductor layer in a vertical direction and including a memory cell array electrically connected to the peripheral circuit. The first semiconductor layer includes a page buffer area in which a page buffer circuit is disposed, the second semiconductor layer includes a cell area in which a plurality of bit lines is arranged at regular intervals along a first direction, and a length in the first direction of the page buffer area is different from a length in the first direction of the cell area.